Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.1 μm complementary metal–oxide–semiconductor (CMOS) technology. A systematic consideration of the required properties of gate dielectrics indicates that the key guidelines for selecting an alternative gate dielectric are (a) permittivity, band gap, and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. A review of current work and literature in the area of alternate gate dielectrics is given. Based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward success...

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High-κ gate dielectrics: Current status and materials properties considerations

Learn the basic properties and designs of modern VLSI devices, as well as the factors affecting performance, with this thoroughly updated second edition. The first edition has been widely adopted as a standard textbook in microelectronics in many major US universities and worldwide. The internationally-renowned authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices. Equations and parameters provided are checked continuously against the reality of silicon data, making the book equally useful in practical transistor design and in the classroom. Every chapter has been updated to include the latest developments, such as MOSFET scale length theory, high-field transport model, and SiGe-base bipolar devices.

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Fundamentals of Modern VLSI Devices

Atomic layer deposition(ALD), a chemical vapor deposition technique based on sequential self-terminating gas–solid reactions, has for about four decades been applied for manufacturing conformal inorganic material layers with thickness down to the nanometer range. Despite the numerous successful applications of material growth by ALD, many physicochemical processes that control ALD growth are not yet sufficiently understood. To increase understanding of ALD processes, overviews are needed not only of the existing ALD processes and their applications, but also of the knowledge of the surface chemistry of specific ALD processes. This work aims to start the overviews on specific ALD processes by reviewing the experimental information available on the surface chemistry of the trimethylaluminum/water process. This process is generally known as a rather ideal ALD process, and plenty of information is available on its surface chemistry. This in-depth summary of the surface chemistry of one representative ALD process aims also to provide a view on the current status of understanding the surface chemistry of ALD, in general. The review starts by describing the basic characteristics of ALD, discussing the history of ALD—including the question who made the first ALD experiments—and giving an overview of the two-reactant ALD processes investigated to date. Second, the basic concepts related to the surface chemistry of ALD are described from a generic viewpoint applicable to all ALD processes based on compound reactants. This description includes physicochemical requirements for self-terminating reactions,reaction kinetics, typical chemisorption mechanisms, factors causing saturation, reasons for growth of less than a monolayer per cycle, effect of the temperature and number of cycles on the growth per cycle (GPC), and the growth mode. A comparison is made of three models available for estimating the sterically allowed value of GPC in ALD. Third, the experimental information on the surface chemistry in the trimethylaluminum/water ALD process are reviewed using the concepts developed in the second part of this review. The results are reviewed critically, with an aim to combine the information obtained in different types of investigations, such as growth experiments on flat substrates and reaction chemistry investigation on high-surface-area materials. Although the surface chemistry of the trimethylaluminum/water ALD process is rather well understood, systematic investigations of the reaction kinetics and the growth mode on different substrates are still missing. The last part of the review is devoted to discussing issues which may hamper surface chemistry investigations of ALD, such as problematic historical assumptions, nonstandard terminology, and the effect of experimental conditions on the surface chemistry of ALD. I hope that this review can help the newcomer get acquainted with the exciting and challenging field of surface chemistry of ALD and can serve as a useful guide for the specialist towards the fifth decade of ALD research.

Surface chemistry of atomic layer deposition: A case study for the trimethylaluminum/water process

The scaling of complementary metal oxide semiconductor transistors has led to the silicon dioxide layer, used as a gate dielectric, being so thin (14?nm) that its leakage current is too large It is necessary to replace the SiO2 with a physically thicker layer of oxides of higher dielectric constant (?) or 'high K' gate oxides such as hafnium oxide and hafnium silicate These oxides had not been extensively studied like SiO2, and they were found to have inferior properties compared with SiO2, such as a tendency to crystallize and a high density of electronic defects Intensive research was needed to develop these oxides as high quality electronic materials This review covers both scientific and technological issues?the choice of oxides, their deposition, their structural and metallurgical behaviour, atomic diffusion, interface structure and reactions, their electronic structure, bonding, band offsets, electronic defects, charge trapping and conduction mechanisms, mobility degradation and flat band voltage shifts The oxygen vacancy is the dominant electron trap It is turning out that the oxides must be implemented in conjunction with metal gate electrodes, the development of which is further behind Issues about work function control in metal gate electrodes are discussed

https://iopscience.iop.org/article/10.1088/0034-4885/69/2/R02/pdf

High dielectric constant gate oxides for metal oxide Si transistors

An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

Starting with a brief review on 0.1-/spl mu/m (100 nm) CMOS status, this paper addresses the key challenges in further scaling of CMOS technology into the nanometer (sub-100 nm) regime in light of fundamental physical effects and practical considerations. Among the issues discussed are: lithography, power supply and threshold voltage, short-channel effect, gate oxide, high-field effects, dopant number fluctuations and interconnect delays. The last part of the paper discusses several alternative or unconventional device structures, including silicon-on-insulator (SOI), SiGe MOSFET's, low-temperature CMOS, and double-gate MOSFET's, which may lead to the outermost limits of silicon scaling.

CMOS scaling into the nanometer regime

Quantum-mechanical modeling of electron tunneling current from the quantized inversion layer of ultra-thin-oxide (<40 /spl Aring/) nMOSFET's is presented, together with experimental verification. An accurate determination of the physical oxide thickness is achieved by fitting experimentally measured capacitance-versus-voltage curves to quantum-mechanically simulated capacitance-versus-voltage results. The lifetimes of quasibound states and the direct tunneling current are calculated using a transverse-resonant method. These results are used to project an oxide scaling limit of 20 /spl Aring/ before the chip standby power becomes excessive due to tunneling currents,.

Quantum-mechanical modeling of electron tunneling current from the inversion layer of ultra-thin-oxide nMOSFET's

Ultrathin high-K metal oxides on silicon: processing, characterization and integration issues

In this paper a review of the more "fundamental" concerns regarding the scaling of the gate dielectric in the ultrathin regime is presented. Material issues are discussed pertaining to the integration of silicon oxynitride and oxide/nitride stacked layers and how such films might reduce or minimize boron penetration problems and address leakage current and reliability concerns. A methodology is presented to calculate device and chip lifetimes for MOS structures on the basis of data extracted from voltage- and temperature-accelerated measurements. Some integration issues regarding higher-k materials are also discussed because of their ability to solve the scaling problem. However, difficulties are involved in integrating them into a CMOS process flow.

Scaling the gate dielectric: materials, integration, and reliability

Atomic hydrogen is found to simultaneously passivate and depassivate silicon dangling bonds at the Si(111)/SiO2 interface at room temperature via the reactions Pb+H0→PbH and PbH+H0→Pb+H2. The passivation reaction occurs more efficiently keeping the steady‐state Pb density at a low value of only 3–6×1011 cm−2 during atomic hydrogen exposure. This low Pb density can only account for a small fraction of the total number of interface states produced by atomic hydrogen.

Douglas A. Buchanan

Papers

CMOS scaling into the nanometer regime

Quantum-mechanical modeling of electron tunneling current from the inversion layer of ultra-thin-oxide nMOSFET's

Ultrathin high-K metal oxides on silicon: processing, characterization and integration issues

Scaling the gate dielectric: materials, integration, and reliability

Passivation and depassivation of silicon dangling bonds at the Si/SiO2 interface by atomic hydrogen