Showing papers by "Takao Aoki published in 1993"
27 Sep 1993
TL;DR: A 1-V high-speed and low-power digital circuit technology with 0.5/spl mu/m multi-threshold CMOS (MT-CMOS) is proposed, which applies both low-th threshold voltage and high-th thresholds voltage MOSFETs in one LSI.
Abstract: A 1-V high-speed and low-power digital circuit technology with 05/spl mu/m multi-threshold CMOS (MT-CMOS) is proposed This technology applies both low-threshold voltage and high-threshold voltage MOSFETs in one LSI Low-threshold voltage MOSFETs enhance speed performance at a supply voltage of 1 V or less High-threshold voltage MOSFETs suppress the stand-by leakage circuit during the sleep period The technology has achieved logic gate characteristics of a 17-ns propagation delay time and 03-/spl mu/W/MHz/gate power dissipation To demonstrate its effectiveness, a standard cell based PLL-LSI was designed as a carrying vehicle An 18-MHz operation at 1 V was obtained using a 05-/spl mu/m MT-CMOS process >
75 citations