High leakage current in deep-submicrometer regimes is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low-power applications. This paper reviews various transistor intrinsic leakage mechanisms, including weak inversion, drain-induced barrier lowering, gate-induced drain leakage, and gate oxide tunneling. Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices. Finally, the paper explores different circuit techniques to reduce the leakage power consumption.

Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits

1-V power supply high-speed low-power digital circuit technology with 0.5-/spl mu/m multithreshold-voltage CMOS (MTCMOS) is proposed. This technology features both low-threshold voltage and high-threshold voltage MOSFET's in a single LSI. The low-threshold voltage MOSFET's enhance speed performance at a low supply voltage of 1 V or less, while the high-threshold voltage MOSFET's suppress the stand-by leakage current during the sleep period. This technology has brought about logic gate characteristics of a 1.7-ns propagation delay time and 0.3-/spl mu/W/MHz/gate power dissipation with a standard load. In addition, an MTCMOS standard cell library has been developed so that conventional CAD tools can be used to lay out low-voltage LSI's. To demonstrate MTCMOS's effectiveness, a PLL LSI based on standard cells was designed as a carrying vehicle. 18-MHz operation at 1 V was achieved using a 0.5-/spl mu/m CMOS process. >

1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS

A five-fold increase in leakage current is predicted with each technology generation. While Dynamic Voltage Scaling (DVS) is known to reduce dynamic power consumption, it also causes increased leakage energy drain by lengthening the interval over which a computation is carried out. Therefore, for minimization of the total energy, one needs to determine an operating point, called the critical speed. We compute processor slowdown factors based on the critical speed for energy minimization. Procrastination scheduling attempts to maximize the duration of idle intervals by keeping the processor in a sleep/shutdown state even if there are pending tasks, within the constraints imposed by performance requirements. Our simulation experiments show that the critical speed slowdown results in up to 5% energy gains over a leakage oblivious dynamic voltage scaling. Procrastination scheduling scheme extends the sleep intervals to up to 5 times, resulting in up to an additional 18% energy gains, while meeting all timing requirements.

Leakage aware dynamic voltage scaling for real-time embedded systems

A 4 mm/sup 2/, two-dimensional (2-D) 8/spl times/8 discrete cosine transform (DCT) core processor for HDTV-resolution video compression/decompression in a 0.3-/spl mu/m CMOS triple-well, double-metal technology operates at 150 MHz from a 0.9-V power supply and consumes 10 mW, only 2% power dissipation of a previous 3.3-V design. Circuit techniques for dynamically varying threshold voltage (VT scheme) are introduced to reduce active power dissipation with negligible overhead in speed, standby power dissipation, and chip area. A way to explore V/sub DD/-V/sub th/ design space is also studied.

A 0.9-V, 150-MHz, 10-mW, 4 mm/sup 2/, 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme

Scaling and power reduction trends in future technologies will cause subthreshold leakage currents to become an increasingly large component of total power dissipation This paper presents several dual-threshold voltage techniques for reducing standby power dissipation while still maintaining high performance in static and dynamic combinational logic blocks MTCMOS sleep transistor sizing issues are addressed, and a hierarchical sizing methodology based on mutual exclusive discharge patterns is presented A dual-V/sub t/ domino logic style that provides the performance equivalent of a purely low-V/sub t/ design with the standby leakage characteristic of a purely high-V/sub t/ implementation is also proposed

Dual-threshold voltage techniques for low-power digital circuits

A 1-V high-speed and low-power digital circuit technology with 05/spl mu/m multi-threshold CMOS (MT-CMOS) is proposed This technology applies both low-threshold voltage and high-threshold voltage MOSFETs in one LSI Low-threshold voltage MOSFETs enhance speed performance at a supply voltage of 1 V or less High-threshold voltage MOSFETs suppress the stand-by leakage circuit during the sleep period The technology has achieved logic gate characteristics of a 17-ns propagation delay time and 03-/spl mu/W/MHz/gate power dissipation To demonstrate its effectiveness, a standard cell based PLL-LSI was designed as a carrying vehicle An 18-MHz operation at 1 V was obtained using a 05-/spl mu/m MT-CMOS process >

1V high-speed digital circuit technology with 0.5/spl mu/m multi-threshold CMOS

The noise margins for CMOS SRAM cells composed of scaled-down MOSFETs are described.



First, an analytical method estimating the noise margins for the CMOS memory cells is proposed. Then scaled-down MOSFET effects, i.e., the mobility degradation and the parasitic resistances will be considered. How each of these effects changes the noise margins will be studied using analytical equations. As a result, it will be determined that the mobility degradation worsens the read margin by considerably reducing the CMOS inverter logic threshold voltage. It will also be determined that the parasitic resistances associated with the drive transistors degrade the read margin.



Finally, equations are derived for the threshold voltage and cell ratio for a given noise margin. Its effectiveness will be demonstrated for 0.2 μm CMOS memory cells.

Static‐noise margin analysis for a scaled‐down CMOS memory cell

Engineering change (EC) is the process of modifying a VLSI design implementation to eliminate design errors, to add new specifica- tions, or to correct design constraint violations. Usually, an EC problem is resolved by using spare cells that have been inserted into unused spaces on a chip. In this paper, we describe an iterative method to determine feasible mapping solutions for an EC problem considering spare cells whose inputs can be connected to Vd dor Gnd. Setting some of the cell inputs to fixed values is referred to as constant insertion. Constant insertion can increase cells' functional flexibility. Our experimental results suggest that constant insertion reduces the area required to find a feasible mapping solution to 80% of that with no constant insertion for the selected EC equations. We also show a procedure for modifying the initial feasible EC solution such that the routing or timing improves.

http://ieeexplore.ieee.org/iel5/43/4785326/04785347.pdf

Spare Cells With Constant Insertion for Engineering Change

To realize a large-capacity, high-speed ECL-compatible SRAM with an access time comparable to that of bipolar ECL RAMs, we have investigated a circuit configuration and optimizing method for SRAMs with peripheral circuits consisting of BiCMOS circuitry except for memory cells on the basis of submicron BiCMOS technology. A predecoder configuration with a bipolar small-amplitude logic circuitry is proposed and the number of predecoders that minimizes the decoder power dissipation is determined. Also, a word-driver circuit that utilizes an NMOS transistor as the driving transistor with BiCMOS inverters is proposed, and its highspeed operation is confirmed. Next, a multiplexer which selects a pair of bit-lines by switching the pull-up voltage with an NMOS transistor and drives data-lines with emitter-follower circuits is proposed and its high-speed operation confirmed. Finally, an optimized memory cell array configuration that minimizes the delay time from the memory cell to the multiplexer is proposed.

Takakuni Douseki

Papers

1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS

1V high-speed digital circuit technology with 0.5/spl mu/m multi-threshold CMOS

Static‐noise margin analysis for a scaled‐down CMOS memory cell

Spare Cells With Constant Insertion for Engineering Change

A high‐speed SRAM using BICMOS technology