This paper describes a single-channel, calibration-free Successive-Approximation-Register (SAR) ADC with a resolution of 10 bits at 240 MS/s. A DAC switching technique and an addition-only digital error correction technique based on the non-binary search are proposed to tackle the static and dynamic non-idealities attributed to capacitor mismatch and insufficient DAC settling. The conversion speed is enhanced, and the power and area of the DAC are also reduced by 40% as a result. In addition, a switching scheme lifting the input common mode of the comparator is proposed to further enhance the speed. Moreover, the comparator employs multiple feedback paths for an enhanced regeneration strength to alleviate the metastable problem. Occupying an active area of 0.003 mm $^{2}$ and dissipating 0.68 mW from 1 V supply at 240 MS/s in 28 nm CMOS, the proposed design achieves an SNDR of 57 dB with low-frequency inputs and 53 dB at the Nyquist input. This corresponds to a conversion efficiency of 4.8 fJ/c.-s. and 7.8 fJ/c.-s. respectively. The DAC switching technique improves the INL and DNL from +1.15/-1.01 LSB and +0.92/-0.28 LSB to within +0.55/-0.45 LSB and +0.45/-0.23 LSB, respectively. This ADC is at least 80% smaller and 32% more power efficient than reported state-of-the-art ADCs of similar resolutions and Nyquist bandwidths larger than 75 MHz.

A 0.003 mm $^{2}$ 10 b 240 MS/s 0.7 mW SAR ADC in 28 nm CMOS With Digital Error Correction and Correlated-Reversed Switching

Growth of III–V nanowires on the [100]-oriented industry standard substrates is critical for future integrated nanowire device development. Here we present an in-depth analysis of the seemingly complex ensembles of epitaxial nanowires grown on InP (100) substrates. The nanowires are categorized into three types as vertical, nonvertical, and planar, and the growth directions, facets, and crystal structure of each type are investigated. The nonvertical growth directions are mathematically modeled using a three-dimensional multiple-order twinning concept. The nonvertical nanowires can be further classified into two different types, with one type growing in the ⟨111⟩ directions and the other in the ⟨100⟩ directions after initial multiple three-dimensional twinning. We find that 99% of the total nanowires are grown either along ⟨100⟩, ⟨111⟩, or ⟨110⟩ growth directions by {100} or {111} growth facets. We also demonstrate relative control of yield of these different types of nanowires, by tuning pregrowth anneal...

Nanowires grown on InP (100): growth directions, facets, crystal structures, and relative yield control.

Multiple-valued logic has a history that goes back to the 1920s. Its flagship symposium was established in 1971. Despite multiple-valued logic's long history, there have been many recent advances, with several important contributions to microelectronic circuits and systems. This tutorial introduction to the area of multiple-valued logic and survey of recent advances focuses on those contemporary aspects of the field that are most relevant to the circuits and systems community.

A Survey and Tutorial on Contemporary Aspects of Multiple-Valued Logic and Its Application to Microelectronic Circuits

Molecular beam epitaxy growth of merging InAs nanowire intersections, that is, a first step toward the realization of a network of such nanowires, is reported. While InAs nanowires play already a leading role in the search for Majorana fermions, a network of these nanowires is expected to promote their exchange and allow for further development of this field. The structural properties of merged InAs nanowire intersections have been investigated using scanning and transmission electron microscope imaging. At the heart of the intersection, a sharp change of the crystal structure from wurtzite to perfect zinc blende is observed. The performed low-temperature conductance measurements demonstrate that the intersection does not impose an obstacle to current transport.

Crystal structure and transport in merged InAs nanowires MBE grown on (001) InAs.

This brief presents a high-speed successive approximation register analog-to-digital converter (ADC) with nonbinary searching technique. By inserting redundancy in the first five decision steps, the digital-to-analog converter (DAC) settling errors can be tolerated and settling time can thus be reduced. In addition, split capacitor technology has also been adopted to further boost the conversion speed. With split switching method, no common mode voltage is needed in DAC reset phase and dynamic offset can be removed as well. Full adder-based encoder is employed to convert the raw 11-bit to 10-bit binary codes, showing less power penalty. The prototype ADC fabricated in 65-nm CMOS achieves 51.1 dB SNDR and 62.3 dB SFDR at 150-MS/s sampling rate. It consumes 1.4 mW, resulting in a Walden figure of merit of 31.8 fJ/conversion step.

A 1.4-mW 10-Bit 150-MS/s SAR ADC With Nonbinary Split Capacitive DAC in 65-nm CMOS

Low-power successive-approximation (SA) analog-to-digital converters (ADCs) are attracting increasing attention these days in biomedical and sensor network applications. The binary search algorithm is one of the basic idea behind how they obtain a binary code representing an analog input. In practice, the imperfectness of analog circuit elements sometimes results in decision errors and decreases the resolution of A/D conversion. Thus, making accurate decisions using imperfect elements is a big challenge. This paper surveys one solution known as non-binary SA with redundancy as well as related topics and its application to state-of-the-art SA ADCs.

Non-binary Successive Approximation Analog-to-Digital Converters: A Survey

Au-assisted growth of InAs NWs by MOVPE growth was investigated. We will discuss the NWs characteristics on GaAs and InP substrate with (111)B and (100) orientation, and on the V/III ratio during the growth. We have observed the growth direction of NWs on each substrates and confirmed that the surface diffusion have relation to the diameter of NWs. In the GaAs (111)B substrate, the diameter and length of NWs were depended on the local density of NWs. Furthermore, the tapered NWs were decreased by lowering the V/III ratio. (© 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

Au‐assisted growth of InAs nanowires on GaAs(111)B, GaAs(100), InP(111)B, InP(100) by MOVPE

Today, nanowire devices are referred to as a qualified successor of CMOS electronics. Both a performance superior to silicon (Si) MOSFETs and a rational, cost-efficient technique to implement multiple nanowire devices into circuits are recommended. We propose to transfer the nanowires from a growth substrate onto a carrier or host substrate using field-assisted self-assembly. This approach allows for the implementation of epitaxial nanowire independent of the choice of growth substrate and its crystal orientation. It avoids any constraints of high qualitative nanowire growth which the process needs and limitations of circuit fabrication.

InAs Nanowire Circuits Fabricated by Field-Assisted Self-Assembly on a Host Substrate

Preheating temperature and growth temperature dependence of InP nanowires grown by self-catalytic VLS mode on InP substrate

Energy efficiency of multi-bit eS modulators has been investigated in terms of a normalized power dissipation, which is commonly referred to as the figure-of-merit (FOM). The multi-bit modulators are designed by adding a multi-level comparator and feedback path to a conventional inverter-based modulator. The FOM is estimated by transistor-level circuit simulation assuming a 0.18-µm standard CMOS technology. In the present 3-bit modulator, the FOM is improved by more than a factor of two compared with a conventional 1-bit one. By using the multi-level comparator, the smaller quantization error reduces the settling time in the integrators, and then improves the energy efficiency.

Takao Waho

Papers

Non-binary Successive Approximation Analog-to-Digital Converters: A Survey

Au‐assisted growth of InAs nanowires on GaAs(111)B, GaAs(100), InP(111)B, InP(100) by MOVPE

InAs Nanowire Circuits Fabricated by Field-Assisted Self-Assembly on a Host Substrate

Preheating temperature and growth temperature dependence of InP nanowires grown by self-catalytic VLS mode on InP substrate

Energy Efficiency of Multi-bit delta-sigma Modulators Using Inverter-based Integrators