A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Top layers of metal for high performance IC's

A solid-state imaging device includes: a pixel region in which a plurality of pixels composed of a photoelectric conversion section and a pixel transistor is arranged; an on-chip color filter; an on-chip microlens; and a multilayer interconnection layer in which a plurality of layers of interconnections is formed through an interlayer insulating film. The solid-state imaging device further includes a light-shielding film formed through an insulating layer in a pixel boundary of a light receiving surface in which the photoelectric conversion section is arranged.

Solid-state imaging device, method of manufacturing the same, and electronic apparatus

A CMOS image sensor architecture with built-in single-shot compressed sensing is described. The image sensor employs a conventional 4-T pixel and per-column ΣΔ ADCs. The compressed sensing measurements are obtained via a column multiplexer that sequentially applies randomly selected pixel values to the input of each ΣΔ modulator. At the end of readout, each ADC outputs a quantized value of the average of the pixel values applied to its input. The image is recovered from the random linear measurements off-chip using numerical optimization algorithms. To demonstrate this architecture, a 256x256 pixel CMOS image sensor is fabricated in 0.15 μm CIS process. The sensor can operate in compressed sensing mode with compression ratio 1/4, 1/8, or 1/16 at 480, 960, or 1920 fps, respectively, or in normal capture mode with no compressed sensing at a maximum frame rate of 120 fps. Measurement results demonstrate capture in compressed sensing mode at roughly the same readout noise of 351 μVrms and power consumption of 96.2 mW of normal capture at 120 fps. This performance is achieved with only 1.8% die area overhead. Image reconstruction shows modest quality loss relative to normal capture and significantly higher image quality than downsampling.

/pdf/cmos-image-sensor-with-per-column-sd-adc-and-programmable-4fjz1c6coh.pdf

CMOS Image Sensor With Per-Column ΣΔ ADC and Programmable Compressed Sensing

A solid-state imaging device includes pixel cells that are formed on a substrate having a first substrate surface side, on which light is irradiated, and a second substrate surface side, on which elements are formed, and separated by an adjacent cell group and an element separation layer for each of the pixel cells or with plural pixel cells as a unit Each of the pixel cells has a first conductive well formed on the first substrate surface side and a second conductive well formed on the second substrate surface side The first conductive well receives light from the first substrate surface side and has a photoelectric conversion function and a charge accumulation function for the received light A transistor that detects accumulated charges in the first conductive well and has a threshold modulation function is formed in the second conductive well

Solid-state imaging device and camera

Digital image sensors in hemispherical geometries offer unique imaging advantages over their planar counterparts, such as wide field of view and low aberrations. Deforming miniature semiconductor-based sensors with high-spatial resolution into such format is challenging. Here we report a simple origami approach for fabricating single-crystalline silicon-based focal plane arrays and artificial compound eyes that have hemisphere-like structures. Convex isogonal polyhedral concepts allow certain combinations of polygons to fold into spherical formats. Using each polygon block as a sensor pixel, the silicon-based devices are shaped into maps of truncated icosahedron and fabricated on flexible sheets and further folded either into a concave or convex hemisphere. These two electronic eye prototypes represent simple and low-cost methods as well as flexible optimization parameters in terms of pixel density and design. Results demonstrated in this work combined with miniature size and simplicity of the design establish practical technology for integration with conventional electronic devices.

/pdf/origami-silicon-optoelectronics-for-hemispherical-electronic-3tvi3ry5do.pdf

Origami silicon optoelectronics for hemispherical electronic eye systems

The Multichip LSI (MCL) comprised of both an embedded 123MHz CPU and a 64Mb memory in one package is introduced 1300 signal lines are directly connected by microbumps between the two chips and achieve 160Gb/s signal interface performance Both the CPU and memory are fabricated in a 015/spl mu/m CMOS technology

A 160Gb/s interface design configuration for multichip LSI

To provide a back-illuminated type solid-state imaging device capable of color separation of pixels without using a color filter, and a camera module and an electronic equipment module which incorporate the solid-state imaging device. A solid-state imaging device including: a photoelectric conversion element PD formed in a semiconductor substrate 22 ; a reading-out part which reads out signal charges from the photoelectric conversion element PD formed on one surface side of the semiconductor substrate 22 ; the other surface of the semiconductor substrate 22 made to a light incidence surface; and a pixel which exclusively makes light of a specific wavelength or longer photoelectrically converted, by adjusting pn junction depths h 2 [ h 2 r, h 2 g, h 2 b] between the photoelectric conversion element PD and an accumulation layer 28 on the light incidence surface side. A camera module and an electronic equipment module which incorporate the solid-state imaging device.

Solid-state imaging device, camera module and electronic equipment module

A solid-state image pickup device 1 according to the present invention includes a semiconductor substrate 2 on which a pixel 20 composed of a photodiode 3 and a transistor is formed. The transistor comprising the pixel 20 is formed on the surface of the semiconductor substrate, a pn junction portion formed between high concentration regions of the photodiode 3 is provided within the semiconductor substrate 2 and a part of the pn junction portion of the photodiode 3 is extended to a lower portion of the transistor formed on the surface of the semiconductor substrate 2 . According to the present invention, there is provided a solid-state image pickup device in which a pixel size can be microminiaturized without lowering a saturated electric charge amount (Qs) and sensitivity.

Solid-state image pickup device

A 3.2-MP four-directional polarization image sensor with air-gap wire-grid polarizer is described. The image sensor was fabricated using a wafer process and incorporates back-illumination and an antireflection layer to minimize optical flaring and ghosting problems. In testing, the sensor achieved a polarization transmittance of 63.3% and an extinction ratio of 85 at 550 nm, thereby outperforming conventional polarization sensors. The proposed sensor also exhibited good oblique-incidence characteristics, even with small polarization pixels of $2.5~\mu \text{m}$ . Based on these results, the proposed image sensor is suitable for various megapixel fusion-imaging applications, such as reducing surface reflections, highly accurate depth mapping, and condition-robust surveillance.

3.2-MP Back-Illuminated Polarization Image Sensor With Four-Directional Air-Gap Wire Grid and 2.5- $\mu$ m Pixels

Rolling-shutter CMOS image sensors (CISs) are widely used [1,2]. However, the distortion of moving subjects remains an unresolved problem, regardless of the speed at which these sensors are operated. It has been reported that by adopting in-pixel analog memory (MEM) in pixels, a global shutter (GS) can be achieved by saving all pixels simultaneously as stored charges [3,4]. However, as signals from a storage unit are read in a column-wise sequence, a light-shielding structure is required for the MEM to suppress the influence of parasitic light during the reading period. Pixel-parallel ADCs have been reported as methods of implementing GS on a circuit [5,6]. However, these techniques have not been successful in operations on megapixels because they do not address issues such as the timing constraint for reading and writing a digital signal to and from an ADC in a pixel owing to increase in the number of pixels and the increase in the total power consumption of massively parallel comparators (CMs).

Takayuki Ezaki

Papers

A 160Gb/s interface design configuration for multichip LSI

Solid-state imaging device, camera module and electronic equipment module

Solid-state image pickup device

3.2-MP Back-Illuminated Polarization Image Sensor With Four-Directional Air-Gap Wire Grid and 2.5- $\mu$ m Pixels

A back-illuminated global-shutter CMOS image sensor with pixel-parallel 14b subthreshold ADC