T
Takeshi Takayama
Researcher at Fujitsu
Publications - 6
Citations - 496
Takeshi Takayama is an academic researcher from Fujitsu. The author has contributed to research in topics: Successive approximation ADC & Comparator. The author has an hindex of 5, co-authored 6 publications receiving 473 citations.
Papers
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Proceedings ArticleDOI
A 10b 50MS/s 820µW SAR ADC with on-chip digital calibration
TL;DR: This ADC is designed with on-chip digital calibration techniques, comparator offset calibration, CDAC linearity error calibration and internal clock frequency control to compensate for the PVT delay variation.
Proceedings ArticleDOI
Split capacitor DAC mismatch calibration in successive approximation ADC
Yanfei Chen,Xiaolei Zhu,Hirotaka Tamura,Masaya Kibune,Yasumoto Tomita,Takayuki Hamada,Masato Yoshioka,Kiyoshi Ishikawa,Takeshi Takayama,Junji Ogawa,Sanroku Tsukamoto,Tadahiro Kuroda +11 more
TL;DR: A split capacitor DAC calibration method is proposed that a bridge capacitor larger than conventional design allows a tunable capacitor to compensate for mismatch and a comparator with digital timing control offset cancellation is proposed.
Journal ArticleDOI
A 10-b 50-MS/s 820- $\mu $ W SAR ADC With On-Chip Digital Calibration
TL;DR: This 10-b 50-MSamples/s SAR analog-to-digital converter (ADC) features on-chip digital calibration techniques, comparator offset cancellation, a capacitor digital- to-analog converter (CDAC) linearity calibration, and internal clock control to compensate for PVT variations.
Journal ArticleDOI
Split Capacitor DAC Mismatch Calibration in Successive Approximation ADC
Yanfei Chen,Xiaolei Zhu,Hirotaka Tamura,Masaya Kibune,Yasumoto Tomita,Takayuki Hamada,Masato Yoshioka,Kiyoshi Ishikawa,Takeshi Takayama,Junji Ogawa,Sanroku Tsukamoto,Tadahiro Kuroda +11 more
TL;DR: A split CDAC mismatch calibration method using a bridge capacitor larger than conventional design so that a tunable capacitor can be added in parallel with the lower-weight capacitor array to compensate for mismatches.
Patent
Comparison circuit and analog-to-digital conversion device
TL;DR: In this paper, a comparison circuit comprising an input circuit including a first transistor for receiving a first signal, and a second transistor to receive a second signal was presented, where a latch for amplifying potential difference between the first current route and the second current route was introduced.