A 1.2 V 10-bit 100 MS/s Successive Approximation (SA) ADC is presented. The scheme achieves high-speed and low-power operation thanks to the reference-free technique that avoids the static power dissipation of an on-chip reference generator. Moreover, the use of a common-mode based charge recovery switching method reduces the switching energy and improves the conversion linearity. A variable self-timed loop optimizes the reset time of the preamplifier to improve the conversion speed. Measurement results on a 90 nm CMOS prototype operated at 1.2 V supply show 3 mW total power consumption with a peak SNDR of 56.6 dB and a FOM of 77 fJ/conv-step.

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A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS

Neuromorphic computing has come to refer to a variety of brain-inspired computers, devices, and models that contrast the pervasive von Neumann computer architecture This biologically inspired approach has created highly connected synthetic neurons and synapses that can be used to model neuroscience theories as well as solve challenging machine learning problems The promise of the technology is to create a brain-like ability to learn and adapt, but the technical challenges are significant, starting with an accurate neuroscience model of how the brain works, to finding materials and engineering breakthroughs to build devices to support these models, to creating a programming framework so the systems can learn, to creating applications with brain-like capabilities In this work, we provide a comprehensive survey of the research and motivations for neuromorphic computing over its history We begin with a 35-year review of the motivations and drivers of neuromorphic computing, then look at the major research areas of the field, which we define as neuro-inspired models, algorithms and learning approaches, hardware and devices, supporting systems, and finally applications We conclude with a broad discussion on the major research topics that need to be addressed in the coming years to see the promise of neuromorphic computing fulfilled The goals of this work are to provide an exhaustive review of the research conducted in neuromorphic computing since the inception of the term, and to motivate further work by illuminating gaps in the field where new research is needed

A Survey of Neuromorphic Computing and Neural Networks in Hardware.

This paper describes an ultra-low power SAR ADC for medical implant devices. To achieve the nano-watt range power consumption, an ultra-low power design strategy has been utilized, imposing maximum simplicity on the ADC architecture, low transistor count and matched capacitive DAC with a switching scheme which results in full-range sampling without switch bootstrapping and extra reset voltage. Furthermore, a dual-supply voltage scheme allows the SAR logic to operate at 0.4 V, reducing the overall power consumption of the ADC by 15% without any loss in performance. The ADC was fabricated in 0.13-μm CMOS. In dual-supply mode (1.0 V for analog and 0.4 V for digital), the ADC consumes 53 nW at a sampling rate of 1 kS/s and achieves the ENOB of 9.1 bits. The leakage power constitutes 25% of the 53-nW total power.

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A 53-nW 9.1-ENOB 1-kS/s SAR ADC in 0.13- $\mu$ m CMOS for Medical Implant Devices

Although charge-redistribution successive approximation (SAR) ADCs are highly efficient, comparator noise and other effects limit the most efficient operation to below 10-b ENOB. This work introduces an oversampling, noise-shaping SAR ADC architecture that achieves 10-b ENOB with an 8-b SAR DAC array. A noise-shaping scheme shapes both comparator noise and quantization noise, thereby decoupling comparator noise from ADC performance. The loop filter is comprised of a cascade of a two-tap charge-domain FIR filter and an integrator to achieve good noise shaping even with a low-quality integrator. The prototype ADC is fabricated in 65-nm CMOS and occupies a core area of 0.03 mm2. Operating at 90 MS/s, it consumes 806 μW from a 1.2-V supply.

A 90-MS/s 11-MHz-Bandwidth 62-dB SNDR Noise-Shaping SAR ADC

Rapid growth in the demand for “Green-IT” or medical applications requires power efficient ADCs. SAR ADC power scales with CMOS technology because it does not need operational amplifiers, which are getting difficult to design in deeply scaled CMOS. Recent published SAR ADCs have no static current, which improves energy efficiency [1, 2]. Split capacitor digital-to-analog converter (CDAC) is one of the best architectures for high resolution SAR ADC, but is very sensitive to the splitting capacitor because of its fractional value and parasitic. Conventional SAR ADC needs approximately 10 times faster external clock if it has no internal clock generator. However the internal SAR clock generation enables the external clock frequency to be the same as the sampling rate, but suffers from unstable operation caused by large PVT delay variation. This ADC is designed with on-chip digital calibration techniques, comparator offset calibration, CDAC linearity error calibration and internal clock frequency control to compensate for the PVT variation. The ADC is integrated in 65nm CMOS and achieved 10b at 50MS/s while consuming 820µW from a 1.0V supply.

A 10b 50MS/s 820µW SAR ADC with on-chip digital calibration

A split capacitor DAC calibration method is proposed that a bridge capacitor larger than conventional design allows a tunable capacitor to compensate for mismatch. To guarantee proper calibration, a comparator with digital timing control offset cancellation is proposed. An 8-bit successive approximation ADC with 4b+4b split capacitor DAC calibration has been implemented in 65nm CMOS, achieving 0.3LSB DNL and INL with 180fF input capacitance.

Split capacitor DAC mismatch calibration in successive approximation ADC

Charge redistribution based successive approximation (SA) analog-to-digital converter (ADC) has the advantage of power efficiency. Split capacitor digital-to-analog converter (CDAC) technique implements two sets of binary-weighted capacitor arrays connected by a bridge capacitor so as to reduce both input load capacitance and area. However, capacitor mismatches degrade ADC performance in terms of DNL and INL. In this work, a split CDAC mismatch calibration method is proposed. A bridge capacitor larger than conventional design is implemented so that a tunable capacitor can be added in parallel with the lower-weight capacitor array to compensate for mismatches. To guarantee correct CDAC calibration, comparator offset is cancelled using a digital timing control charge compensation technique. To further reduce the input load capacitance, an extra unit capacitor is added to the higher-weight capacitor array. Instead of the lower-weight capacitor array, the extra unit capacitor and the higher-weight capacitor array sample analog input signal. An 8-bit SA ADC with 4-bit + 4-bit split CDAC has been implemented in a 65nm CMOS process. The ADC has an input capacitance of 180fF and occupies an active area of 0.03mm2. Measured results of +0.2/-0.3LSB DNL and +0.3/-0.3LSB INL have been achieved after calibration.

Split Capacitor DAC Mismatch Calibration in Successive Approximation ADC

A principle of charge compensation approach for comparator offset control is analyzed. A dynamic offset control technique that employs charge compensation by timing control is proposed for comparator design in scaled CMOS technology. The analysis has been verified by fabricating a 65 nm CMOS 1.2 V 1 GHz comparator that occupies 25 times 65 mum2 and consumes 380 muW. Circuits for offset control occupies 21% of the areas and 12% of the power consumption of the whole comparator chip.

A dynamic offset control technique for comparator design in scaled CMOS technology

The capacitor digital-to-analog converter (CDAC) which affects the system performance of speed and linearity occupies the most area in successive approximation register (SAR) analog-to-digital converter (ADC). The performance of tri-level SAR ADC is well balanced between power and speed comparing to the conventional CDAC based architecture. In order to further improve the ADC performance in light of area and energy efficiencies, a partially asymmetric tri-level CDAC design technique is proposed to save the silicon cost and power as well. Combining the asymmetric CDAC approach with the tri-level charge redistribution technique makes it possible for the SAR ADC to achieve a 9-bit resolution with 4-bit + 3-bit split capacitor arrays. A 9-bit SAR ADC with CDAC calibration has been implemented in a 65nm CMOS technology and it achieves a peak SNDR of 50.1 dB and consumes 1.26 mW from a 1.2-V supply, corresponding to a FOM of 45fJ/conv.-step. The static performance of +0.4/−0.5 LSB DNL and +0.5/−0.7 LSB INL is achieved. The ADC has input capacitance of 180 fF and occupies an active area of 0.1*0.13 mm2.

A 9-bit 100MS/s tri-level charge redistribution SAR ADC with asymmetric CDAC array

A 1GHz monolithic high spectrum purity fractional-N frequency synthesizer with a 3-b third-order /spl Delta//spl Sigma/ modulator is implemented. A combined tuning technique of analog tuning and digital tuning is used to improve the phase noise of the frequency synthesizer. The power supply configuration is optimized to reduce the supply noise coupling, to improve the linearity of PFD and to increase the tuning range of the VCO. The on-chip VCO with a small gain utilizes the tail current source filtering technique to achieve a low phase noise, but it still keeps 100MHz tuning range due to the introduction of the on-chip digital controlled switched capacitor array. A pseudorandom sequence with a length of 2/sup 24/ is used for the 3-b third-order /spl Delta//spl Sigma/ modulator with LSB dithering resulting in less than 0.001ppm frequency resolution. The frequency synthesizer has been integrated on one chip in CMOS 0.18/spl mu/m process, the simulated results show the frequency synthesizer has a 14kHz loop bandwidth and a high spectrum purity, the maximum in-band phase noise is -106dBc/Hz, the phase noise is lower than -120dBc/Hz at 100kHz offset. And the frequency synthesizer has a fast settling time which is about 160/spl mu/s.

Xiaolei Zhu

Papers

Split capacitor DAC mismatch calibration in successive approximation ADC

Split Capacitor DAC Mismatch Calibration in Successive Approximation ADC

A dynamic offset control technique for comparator design in scaled CMOS technology

A 9-bit 100MS/s tri-level charge redistribution SAR ADC with asymmetric CDAC array

1GHz monolithic high spectrum purity fractional-N frequency synthesizer with a 3-b third-order delta-sigma modulator