Proceedings ArticleDOI
A 1.8 V 36 mW DSP for the half-rate speech codec
Taketora Shiraishi,Koji Kawamoto,K. Ishikawa,Hisakazu Sato,F. Asai,Eiichi Teraoka,Toru Kengaku,Hidehiro Takata,T. Tokuda,K. Nishida,K. Saitoh +10 more
- pp 371-374
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TLDR
A low-power 16-bit DSP has been developed to realize a low bit-rate speech codec and the PDC half-ratespeech codec is implemented in the DSP with 36 mW at 1.8 V.Abstract:
A low-power 16-bit DSP has been developed to realize a low bit-rate speech codec A dual datapath architecture and low-power circuit design techniques are employed to reduce power consumption The PDC half-rate speech codec is implemented in the DSP with 36 mW at 18 Vread more
Citations
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Proceedings ArticleDOI
Ultra-low-power domain-specific multimedia processors
A. Abnous,Jan M. Rabaey +1 more
TL;DR: This work presents a hybrid architecture template that can be used to implement ultra-low-power programmable processors for signal processing applications.
Proceedings ArticleDOI
High-speed cascode sensing scheme for 1.0 V contact-programming mask ROM
TL;DR: In this paper, a low-voltage contact-programming mask ROM was designed which utilizes a cascode sense amplifier (S/A) and a dummy S/A controlled the bit-line pre-charging period to operate the read S /A quickly in spite of high programmed-data-dependence of the bit line capacitance.
Proceedings ArticleDOI
A structural approach for designing performance enhanced signal processors: a 1-MIPS GSM fullrate vocoder case study
TL;DR: A structural approach is presented to show how datapath add-ons or tailorizations can be applied to increase the DSP's performance.
Proceedings ArticleDOI
A low-power DSP core architecture for low bitrate speech codec
TL;DR: A VLSI implementation of a low-power DSP is described, which is dedicated to the G.723.1 low bitrate speech codec and based on dual multiply accumulators, rounding and saturation mechanisms, and two-banked on-chip memory.
Proceedings ArticleDOI
Low-power implementation of H.324 audiovisual codec dedicated to mobile computing
TL;DR: A VLSI implementation of the H.324 audiovisual codec is described, using 0.35 /spl mu/m CMOS 4LM technology, which contains totally 420 K transistors with the dissipation of 224.32 mW from single 3.3 V supply.
References
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Journal ArticleDOI
Low-power CMOS digital design
TL;DR: In this paper, techniques for low power operation are presented which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations to reduce power consumption in CMOS digital circuits while maintaining computational throughput.
Journal Article
Low-Power CMOS Digital Design
TL;DR: An architecturally based scaling strategy is presented which indicates that the optimum voltage is much lower than that determined by other scaling considerations, and is achieved by trading increased silicon area for reduced power consumption.
Proceedings ArticleDOI
A 16 bit low-power-consumption digital signal processor using a 80 MOPS redundant binary MAC
Hideyuki Kabuo,M. Okamoto,R. Tanaka,H. Yasoshima,S. Marui,M. Yamasaki,T. Sugimura,K. Ueda,T. Ishikawa,H. Suzuki,R. Asahi +10 more
TL;DR: This paper describes a 16b fixed point digital signal processor (DSP), especially a variable pipeline multiply-accumulate (MAC) unit using a redundant binary representation that improves 9.8% in power consumption and 249b in operation speed at multiply and multiply- Accumulate operation over a conventional MAC unit.