An experimental technique is described for observing the effects of switching transients in digital MOS circuits that perturb analog circuits integrated on the same die by means of coupling through the substrate Various approaches to reducing substrate crosstalk (the use of physical separation of analog and digital circuits, guard rings, and a low-inductance substrate bias) are evaluated experimentally for a CMOS technology with a substrate comprising an epitaxial layer grown on a heavily doped bulk wafer Observations indicate that reducing the inductance in the substrate bias is the most effective Device simulations are used to show how crosstalk propagates via the heavily doped bulk and to predict the nature of substrate crosstalk in CMOS technologies integrated in uniform, lightly doped bulk substrates, showing that in such cases the substrate noise is highly dependent on layout geometry A method of including substrate effects in SPICE simulations for circuits fabricated on epitaxial, heavily doped substrates is developed >

Experimental Results and Modeling Techniques for Substrate Noise in Mixed-Signal Integrated Circuits

Three dimensional (3D) stacking of memory chips is a promising direction for implementing memory systems in mobile applications and for low-cost high-performance computation. The requirements are extremely low power consumption, high data bandwidth, stability and scalability of operation, as well as large storage capacity with a small footprint. A digital control chip at the base of the stack is needed to efficiently access the 3D memory hierarchy, as well as to emulate a standard memory interface for compatibility. The overall performance and yields of a 3D system are constrained by vertical communication channels among the stacked chips, as well as the connections to the PCB. However, the empirical models presently used in the design stage do not properly represent the electrical and mechanical properties and performance variations of through silicon vias (TSVs) and microbumps (μBumps). What is needed are circuit techniques that handle such uncertainties to enable the creation of robust 3D data links. This paper presents a complete test vehicle for TSV-based wide I/O data communication in a three-tier 3D chip stack assembled in a BGA package. In-place eye-diagram and waveform capturers are mounted in an active silicon interposer to characterize vertical signaling through the chain of TSVs and μBumps.

A 100GB/s wide I/O with 4096b TSVs through an active silicon interposer with in-place waveform capturing

An on-chip waveform capturer exhibits 8.8-bit effective accuracy at a 5-ps timing resolution and 190 μV voltage, with an effective bandwidth of 700 MHz in a 65-nm CMOS prototype. Voltage by a digital-to-analog converter with selectable slopes and offsets is linearly translated into timing, that is used for strobing a waveform. Programmable timing and voltage generation as well as selective input channels are intended for exhaustive power noise measurements on power delivery networks (PDNs) across rail-to-rail voltage domains in a chip. The measurement procedures are totally governed by an embedded controller. The waveform capturer, in combination with a PDN exciter, realizes in situ derivation of resonance parameters by assembling oscillatory waveforms. A power noise reduction of more than 50% is accomplished through on-chip PDN diagnosis, in which the operation frequencies are selected such that the periodical appearance of PDN resonance is prevented.

An On-Chip Waveform Capturer and Application to Diagnosis of Power Delivery in SoC Integration

An on-chip waveform capturer exhibits 8.8-bit effective accuracy at a 5-ps timing resolution and 190 μ V voltage, with an effective bandwidth of 700 MHz in a 65-nm CMOS prototype. Voltage by a digital-to-analog converter with selectable slopes and offsets is linearly translated into timing, that is used for strobing a waveform. Programmable timing and voltage generation as well as selective input channels are intended for exhaustive power noise measurements on power delivery networks (PDNs) across rail-to-rail voltage domains in a chip. The measurement procedures are totally governed by an embedded controller. The waveform capturer, in combination with a PDN exciter, realizes in situ derivation of resonance parameters by assembling oscillatory waveforms. A power noise reduction of more than 50% is accomplished through on-chip PDN diagnosis, in which the operation frequencies are selected such that the periodical appearance of PDN resonance is prevented.

An on-chip multichannel waveform monitoring technique enhances built-in test and diagnostic capabilities of systems- on-a-chip (SoC) integration. The proposed multichannel monitor includes multiple probing front-end modules and a single shared waveform acquisition kernel that consists of an incremental variable step delay generator and an incremental reference voltage generator, featuring adaptive sample time generation for the operation of a target circuit and unidirectional waveform acquisition flow for area-efficient control. A 16-channel prototype in 0.18-mum CMOS technology demonstrated on-chip waveform acquisition at 40-ps and 200-muV resolutions. Combined on- and off-chip streamed-bit processing achieves background continuous waveform acquisition at 260 ms per single timing point for repetitive signals, while eliminating the integration of on-die high-capacity memory. A 700 mum times 600 mum area was occupied by a waveform acquisition kernel and an additional 60 mum times 100 mum area for each front-end module. The developed on-chip multichannel waveform monitoring technique is waveform accurate, area efficient, and suitable for diagnosis toward power supply and signal integrity in analog and digital circuits in mixed-signal SoC integration.

An On-Chip Multichannel Waveform Monitor for Diagnosis of Systems-on-a-Chip Integration

An on-chip waveform capturing technique demonstrates 8.5 ENOB and 62.7 dB SFDR at 200 Ms/s for analog signals with 25-MHz bandwidth and 2.5 V rail-to-rail offset DC level, suitable for testing and self diagnosis of a mixed-signal chip. The area of 0.004mm2 in a 90 nm CMOS chip is only required for the integration of probing front end circuitry, with the help of an efficient discretization algorithm on a digital data processing chain involving on-chip logic paths, an off-chip 8 bit micro controller, and PC. Waveform acquisition at the system throughput of 1.9 transaction/point is achieved, by minimizing the number of slow-speed transactions between external measurement equipments and PC.

An on-chip waveform capturing technique pursuing minimum cost of integration

On-chip waveform capture exhibits the resolution of 10 ps and 200 µV with 1024 steps, and SFDR of 63.2dB in 700-MHz signal bandwidth of interest. On-chip signal probing as well as digital waveform processing are merged in systems-on-chip (SoC) integration. An exciter is combined for on-chip derivation of LCR parasitics from oscillatory waveforms of a power delivery network that are effectively seen by SoC circuits.

On-chip waveform capture and diagnosis of power delivery in SoC integration

A highly multi-channel on-chip signal monitor establishes analog circuit diagnosis against environmental disturbances in SoCs. A 0.18-mum CMOS experimental on-chip test bench embeds an array of 53 distributed probes followed by a single shared waveform acquisition kernel, enabling on- and off-chip cooperative high-throughput digitization of 330 ms per sample point with adaptive 10-bit timing and voltage resolutions at the minimum LSB of 100 ps and 400 V. Analog signals of interest in a 1.5-bit conversion stage of pipeline ADC are evaluated in terms of their response to substrate noises globally existing in a chip. Through this on-chip diagnosis we derive in-depth findings relating to dynamic, large-signal, and sensitive behaviors of analog circuits in a real SoC environment, far beyond simulations with inevitably limited capacity

Takushi Hashida

Papers

An On-Chip Waveform Capturer and Application to Diagnosis of Power Delivery in SoC Integration

An On-Chip Waveform Capturer and Application to Diagnosis of Power Delivery in SoC Integration

An on-chip waveform capturing technique pursuing minimum cost of integration

On-chip waveform capture and diagnosis of power delivery in SoC integration

On-Chip Analog Circuit Diagnosis in Systems-on-Chip Integration