A lithographic apparatus configured to project a patterned beam of radiation onto a target portion of a substrate is disclosed. The apparatus includes a first radiation dose detector and a second radiation dose detector, each detector comprising a secondary electron emission surface configured to receive a radiation flux and to emit secondary electrons due to the receipt of the radiation flux, the first radiation dose detector located upstream with respect to the second radiation dose detector viewed with respect to a direction of radiation transmission, and a meter, connected to each detector, to detect a current or voltage resulting from the secondary electron emission from the respective electron emission surface.

Lithographic apparatus, and device manufacturing method

Advancements in optical lithography tools, processes, and patterning materials have been critical to the continued performance increases of semiconductor devices as well as to the overall economics of the semiconductor industry.1 Reducing the wavelength of the source radiation has been a traditional pathway to increase resolution in optical lithography.1-3 In recent years, the technological challenges and the soaring costs associated with developing new exposure tools and new imaging materials have slowed the progress of wavelength scaling, evidenced by the decision not to commercialize 157 nm (F2 excimer) lithography in 2004.4 Rather than reducing the vacuum wavelength of the illumination, the semiconductor industry instead turned to scaling the effective wavelength via immersion lithography to extend the resolution capabilities of 193 nm lithography. Immersion lithography, which utilizes a coupling medium with a refractive index greater than that of air between the last lens element (LLE) and the photoresist, provides an increased depth-of-focus (DOF) and enables imaging systems with numerical apertures greater than one.5-13 This approach is economically attractive since it continues to use large amounts of the existing lithographic tooling infrastructure and patterning materials. In particular, the rapid development and commercialization of 193 nm water immersion lithography helped seal the fate of 157 nm lithography.

Advances in patterning materials for 193 nm immersion lithography.

First and second virtual grates are defined as respective sets of parallel virtual lines extending across a layout area in first and second perpendicular directions, respectively. The virtual lines of the first and second virtual grates correspond to placement locations for layout features in lower and higher chip levels, respectively. Each intersection point between virtual lines of the first and second virtual grates is a gridpoint within a vertical connection placement grid. Vertical connection structures are placed at a number of gridpoints within the vertical connection placement grid so as to provide electrical connectivity between layout features in the lower and higher chip levels. The vertical connection structures are placed so as to minimize a number of different spacing sizes between neighboring vertical connection structures across the vertical connection placement grid, while simultaneously minimizing to an extent possible layout area size. The vertical connection structures may be contacts or vias.

Methods for defining contact grid in dynamic array architecture

A cell circuit and corresponding layout is disclosed to include linear-shaped diffusion fins defined to extend over a substrate in a first direction so as to extend parallel to each other. Each of the linear-shaped diffusion fins is defined to project upward from the substrate along their extent in the first direction. A number of gate level structures are defined to extend in a conformal manner over some of the number of linear-shaped diffusion fins. Portions of each gate level structure that extend over any of the linear-shaped diffusion fins extend in a second direction that is substantially perpendicular to the first direction. Portions of each gate level structure that extend over any of the linear-shaped diffusion fins form gate electrodes of a corresponding transistor. The diffusion fins and gate level structures can be placed in accordance with a diffusion fin virtual grate and a gate level virtual grate, respectively.

Cell circuit and layout with linear finfet structures

A rectangular interlevel connector array (RICA) is defined in a semiconductor chip. To define the RICA, a virtual grid for interlevel connector placement is defined to include a first set of parallel virtual lines that extend across the layout in a first direction, and a second set of parallel virtual lines that extend across the layout in a second direction perpendicular to the first direction. A first plurality of interlevel connector structures are placed at respective gridpoints in the virtual grid to form a first RICA. The first plurality of interlevel connector structures of the first RICA are placed to collaboratively connect a first conductor channel in a first chip level with a second conductor channel in a second chip level. A second RICA can be interleaved with the first RICA to collaboratively connect third and fourth conductor channels that are respectively interleaved with the first and second conductor channels.

Methods for multi-wire routing and apparatus implementing same

There is provided a method of fabricating a semiconductor device whereby fine patterns are formed with high dimensional accuracy by means of multiple exposures, using a phase shift mask and a trim mask Phases are periodically assigned to shifter patterns within a given range from patterns generated with the phase shift mask, respectively

Method for fabricating a semiconductor device

A method of forming a resist pattern through liquid immersion exposure in which exposure is performed such that a liquid film is formed between a substrate for a semiconductor device on which a processed film is formed and an objective lens arranged above the substrate is provided, and the substrate treated with a water-repellent agent solution composed of at least a water-repellent agent and a solvent is exposed to light.

Method of forming resist pattern and semiconductor device manufactured with the same

PROBLEM TO BE SOLVED: To provide a method for forming a resist pattern having a sufficiently-high water-shedding property required in a liquid immesion exposure and a suppressive effect for an exfoliation of a film, and to provide a semiconductor device manufactured by the method. SOLUTION: The embodiment of this invention comprises the steps of arranging an objective lens on a substrate of the semiconductor device with a film to be processed; and forming the resist pattern by the liquid immersion exposure for forming the liquid film between the objective lens and the substrate to exposure. The substrate processed by a water-shedding chemical comprising at least the water shedding agent and the solvent is exposed. COPYRIGHT: (C)2009,JPO&INPIT

Method for forming resist pattern, and semiconductor device manufactured by the method

Non-topcoat (non-TC) resists, which blend hydrophobic additives into a resist polymer, have been proposed by vendors. To minimize the surface free energy, a hydrophobic additive segregates to the surface and forms a layer. The improvement of surface hydrophobicity and the suppression of resist component leaching are achieved by using this segregation layer. Segregation is an unstable physical phenomenon that is influenced by the environment. Hence, the characteristics of segregation layers must be sufficiently understood to use non-TC resists safely and have been thoroughly investigated using various analyses in this study. The results revealed the following: (1) A segregation layer comprising only the hydrophobic additive could form if the additive had low critical surface tension. However, the segregation layer differed from the coating film and exhibited a film density comparable to that of the base polymer. (2) The segregation mostly occurred during spin coating. (3) A non-TC resist should have the optimum film thickness: a thin film exhibited low hydrophobicity, whereas the additive remained in the resist bulk for a thick film. (4) There were no differences in the segregation layer in the central and outer parts of the wafer. When using a non-TC resist, it is necessary to understand the characteristics and note the usage. If it is used with sufficient understanding, it is sure that a non-TC resist can reduce the cost and increase the throughput safely.

Surface Segregation Analysis of Hydrophobic Additive of Non-topcoat Resist

A developing method for immersion lithography is provided, realizing a process that is simple and low-cost and enables high repellency sufficient to allow high-speed scanning. The developing method for immersion lithography improved by inexpensive material without introducing any new facility, a solution to be used in the developing method, and an electronic device formed by using the developing method are provided. The developing method for immersion lithography is a method of developing for immersion lithography of an electronic device with a resist containing a surface segregation agent and chemically-amplified resist, including the step of development with alkali immersion, characterized by the dissolving and removing step, conducted using a dissolving and removing solution that selectively dissolves and removes the surface segregation agent of the resist.

Takuya Hagiwara

Papers

Method for fabricating a semiconductor device

Method of forming resist pattern and semiconductor device manufactured with the same

Method for forming resist pattern, and semiconductor device manufactured by the method

Surface Segregation Analysis of Hydrophobic Additive of Non-topcoat Resist

Developing method for immersion lithography, solvent used for the developing method and electronic device using the developing method