Predictions and measurements of the effect of biaxial strain on the properties of epitaxial ferroelectric thin films and superlattices are reviewed. Results for single-layer ferroelectric films of biaxially strained SrTiO3, BaTiO3, and PbTiO3 as well as PbTiO3/SrTiO3 and BaTiO3/SrTiO3 superlattices are described. Theoretical ap- proaches, including first principles, thermodynamic analysis, and phase-field models, are applied to these biaxially strained materials, the assumptions and limitations of each technique are explained, and the predictions are compared. Measurements of the effect of biax- ial strain on the paraelectric-to-ferroelectric transition temperature (TC) are shown, demonstrating the ability of percent-level strains to shift TC by hundreds of degrees in agreement with the predic- tions that predated such experiments. Along the way, important ex- perimental techniques for characterizing the properties of strained ferroelectric thin films and superlattices, as well as appropriate sub- strates on which to grow them, are mentioned.

/pdf/strain-tuning-of-ferroelectric-thin-films-i3r81086fk.pdf

Strain Tuning of Ferroelectric Thin Films

There is provided a light emitting device in which low power consumption can be realized even in the case of a large screen. The surface of a source signal line or a power supply line in a pixel portion is plated to reduce a resistance of a wiring. The source signal line in the pixel portion is manufactured by a step different from a source signal line in a driver circuit portion. The power supply line in the pixel portion is manufactured by a step different from a power supply line led on a substrate. A terminal is similarly plated to made the resistance reduction. It is desirable that a wiring before plating is made of the same material as a gate electrode and the surface of the wiring is plated to form the source signal line or the power supply line.

Light emitting device and method of manufacturing the same

https://www.cse.iitk.ac.in/users/isaha/Publications/Journals/NC10.pdf/

Artificial neural networks in hardware: A survey of two decades of progress

Recent studies have produced 0.1 × 0.1 μm ferroelectric cells in both bismuth titanate and strontium bismuth tantalate, thus taking thin-film ferroelectric memories into the regime of nanoscale (100 nm or less) devices. A review is presented of deposition, switching, and leakage current in these devices, which are small enough to permit 1 Gbit memories on a standard Si chip.

NANO-phase SBT-family ferroelectric memories

The Self-Organizing Map (SOM) algorithm has attracted an ever increasing amount of interest among researches and practitioners in a wide variety of elds The SOM and a variant of it, the LVQ, have been analyzed extensively, a number of variants of them have been developed and, perhaps most notably, they have been applied extensively within elds ranging from engineering sciences to medicine, biology, and economics We have collected a comprehensive list of 3343 scienti c papers that use the algorithms, have bene ted from them, or contain analyses of them The list is intended to serve as a source for literature surveys We have provided both a thematic and a keyword index to help nding articles of interest

Bibliography of Self-Organizing Map (SOM) Papers: 1981-1997

A semiconductor device comprising an integrated circuit and a capacitor In this capacitor, a bottom electrode, a dielectric film and a top electrode are formed, independently of the integrated circuit, on the interlayer insulating film, and the top electrode and bottom electrode are connected with metal interconnections through contact holes opened in the protective film for protecting the surface of the capacitor In this constitution, either the top electrode or the bottom electrode is connected the bias line of the integrated circuit, and the other is connected to the ground line, so that extraneous emission may be reduced without having to connect the capacitor outside

Semiconductor device having capacitor and manufacturing method thereof

A 64-neuron electrically trainable BiCMOS analog neuroprocessor based on three-layered PDP networks is described. The minimum feedforward propagation time is 10 mu s, equivalent to operation speed of 10/sup 8/ multiplications/s. Analog neuroprocessors with a storage capacitor for the synapse have been studied. The short retention time of the synapse weight has been an obstacle to the development of an analog neurochip. A dynamic refresh technique described here increases the retention time of the synapse weight, leading to a practical implementation of the neuroprocessor. The approach is to refresh the weight charge in the same manner as in DRAMs. All outputs from the synapses on the same column are summed and sent to a neuron cell. The weight from an off-chip digital memory is converted to analog form and then written on the storage capacitor of a synapse selected by x and y decoders. This scheme permits updating the weight by addressing the synapses sequentially. Iteration number in backpropagation learning depends on the operation accuracy of a sigmoid function generator and a multiplier. The network is hardly trained when the multiplier error is larger than 20%. To reduce the error, the neuroprocessor is based on a bipolar-MOS analog circuit, using bipolar transistors for both the multiplier and the sigmoid function generator.<<ETX>>

http://ieeexplore.ieee.org/iel2/120/3337/00110167.pdf

TPM 9.1: A BiCMOS Analog Neural Network with Dynamically Updated Weights

Nonvolatile memory utilizing ferroelectric material is expected to be the ultimate memory due to its theoretical low power operation and fast access. We integrated a ferroelectric thin film using a standard complementary metal-oxide-semiconductor (CMOS) process and evaluated its basic characteristics and reliability including endurance and imprint effect. The film was prepared using a spin-on sol-gel method. A ferroelectric thin film formed using liquid source misted chemical deposition (LSMCD) was found to have almost the same characteristics as those of the film formed by the sol-gel method. No effects of the ferroelectric process on the CMOS transistors were observed. Design of ferroelectric memory cells and applications of the ferroelectric nonvolatile memory have been reviewed.

https://iopscience.iop.org/article/10.1143/JJAP.35.1516/pdf

Ferroelectric nonvolatile memory technology and its applications

Temperature-dependent current-voltage characteristics of fully processed Ba0.7Sr0.3TiO3 thin film capacitors integrated in a charge-coupled device delay-line processor as bypass capacitors were studied. The thin film capacitors with a film thickness of 185 nm were formed by metal-organic decomposition processing. The leakage current measured after completion of the integration process was 1 to 2 orders of magnitude higher than that measured after capacitor patterning. The leakage current at low voltages ( 10 V, 500 kV/cm), the Schottky mechanism plays a dominant role in leakage current, while the Frenkel-Poole emission begins to contribute to the leakage current as the temperature is elevated.

Temperature-Dependent Current-Voltage Characteristics of Fully Processed Ba0.7Sr0.3TiO3 Capacitors Integrated in a Silicon Device

We investigated the origin of retention failure in ferroelectric memories (FeRAMs) with SrBi2(Ta, Nb)2O9 (SBTN) memory cell capacitors by considering the time-dependent behavior of polarization vs. voltage (P-V ) curves of the capacitors during high-temperature storage. Since the SBTN capacitors exhibited no marked decrease in the nonvolatile component of polarization even after high-temperature storage, we focused on the effect of voltage shift observed in P-V curves. We calculated bitline voltage along the storage from the P-V curves and the bitline capacitance, and successfully estimated a decrease in the bitline voltage, which is in agreement with the retention failure in FeRAMs. In addition, the calculation indicated that the lifetime limited by the retention failure in FeRAMs with SBTN capacitors at 125°C exceeds 10 years.

Tatsuo Otsuki

Papers

Semiconductor device having capacitor and manufacturing method thereof

TPM 9.1: A BiCMOS Analog Neural Network with Dynamically Updated Weights

Ferroelectric nonvolatile memory technology and its applications

Temperature-Dependent Current-Voltage Characteristics of Fully Processed Ba0.7Sr0.3TiO3 Capacitors Integrated in a Silicon Device

Voltage Shift Effect on Retention Failure in Ferroelectric Memories