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Patent

Semiconductor device having capacitor and manufacturing method thereof

TLDR
In this paper, a semiconductor device comprising an integrated circuit and a capacitor is described, where either the top electrode or the bottom electrode is connected the bias line of the integrated circuit, and the other is connected to the ground line, so that extraneous emission may be reduced without having to connect the capacitor outside.
Abstract
A semiconductor device comprising an integrated circuit and a capacitor In this capacitor, a bottom electrode, a dielectric film and a top electrode are formed, independently of the integrated circuit, on the interlayer insulating film, and the top electrode and bottom electrode are connected with metal interconnections through contact holes opened in the protective film for protecting the surface of the capacitor In this constitution, either the top electrode or the bottom electrode is connected the bias line of the integrated circuit, and the other is connected to the ground line, so that extraneous emission may be reduced without having to connect the capacitor outside

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Citations
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Patent

Semiconductor device and manufacturing method thereof

TL;DR: In this paper, the problem of making uniform the processed shape of a via (via contact) contact has been addressed, where a semiconductor device comprises a first wiring layer, a second wiring layer formed above the first wires, and a via 20 disposed on a via layer located between the first wiring layers and the second wiring layers.
Patent

Semiconductor memory device having capacitor protection layer and method for manufacturing the same

TL;DR: In this paper, the authors present a method for manufacturing a multi-layer capacitor protection layer for semiconductor memory devices, which consists of at least a blocking layer and a capacitance protection layer, each of which is formed of different materials.
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Semiconductor integrated circuit device and process for manufacturing the same

TL;DR: In this paper, a plurality of first contact holes reaching an n + -type semiconductor area used as the source of a MISFET employed in a logic-DRAM mixture LSI are bored through an insulation layer created over a gate electrode.
Patent

A capacitor for an integrated circuit and method of formation thereof, and a method of adding on-chip capacitors to an integrated circuit

TL;DR: In this article, a capacitor structure and method of forming a capacitance structure for an integrated circuit is provided, comprising a first electrode, capacitor dielectric and top electrode, formed on a passivation layer overlying the interconnect metallization.
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Display apparatus with function which makes gradiation control easier

TL;DR: In this article, luminance data being applied to a data line is set in a drive transistor in the form of a data voltage, and a current corresponding to the data voltage thus set flows to the drive transistor and simultaneously the same current flows to a first current mirror transistor.
References
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Patent

High-dielectric-constant material electrodes comprising thin platinum layers

TL;DR: In this paper, a thin unreactive film was proposed to provide a stable conductive interface between the high-dielectric-constant material layer and the electrode base (e.g. palladium 34).
Patent

Manufacture of semiconductor device

TL;DR: In this article, a first exposure is carried out with a stepped surface A from among at least two stepped surfaces A, B being focused, and a second exposure with the stepped surface B being not focused, at that time, the part facing the not focused is provided with a mask part 22a having a width X+dX larger than the designed value X.
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Low temperature process for depositing oxide layers by photochemical vapor deposition

TL;DR: In this article, a low temperature process for depositing oxide layers on a substrate by photochemical vapor deposition, by exposing the substrate to a selected vapor phase reactant in the presence of photochemically generated neutral (unionized) oxygen atoms.
Patent

Ferroelectric memory cell arrangement having a split capacitor plate structure

TL;DR: In this article, a ferroelectric memory cell architecture was proposed, in which a pair of cells are fabricated so as to share common elements, and where the capacitors are fabricated overlying the associated select transistors, thereby achieving a small-area cell architecture.
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Ozone gas processing for ferroelectric memory circuits

TL;DR: In this article, a method for forming a ferroelectric capacitor for use an integrated circuit establishing one layer over another and then annealing the structure, using an oxygen or ozone anneal, after each layer is established.