A semiconductor device includes a substrate and a number of diffusion regions defined within the substrate. The diffusion regions are separated from each other by a non-active region of the substrate. The semiconductor device includes a number of linear gate electrode tracks defined to extend over the substrate in a single common direction. Each linear gate electrode track is defined by one or more linear gate electrode segments. Each linear gate electrode track that extends over both a diffusion region and a non-active region of the substrate is defined to minimize a separation distance between ends of adjacent linear gate electrode segments within the linear gate electrode track, while ensuring adequate electrical isolation between the adjacent linear gate electrode segments.

Dynamic array architecture

Methods and apparatus for a gate-length biasing methodology for optimizing integrated digital circuits are described. The gate-length biasing methodology replaces a nominal gate-length of a transistor with a biased gate-length, where the biased gate-length includes a bias length that is small compared to the nominal gate-length. In an exemplary embodiment, the bias length is less than 10% of the nominal gate-length.

Gate-length biasing for digital circuit optimization

A method is disclosed for defining a dynamic array section to be manufactured on a semiconductor chip. The method includes defining a peripheral boundary of the dynamic array section. The method also includes defining a manufacturing assurance halo outside the boundary of the dynamic array section. The method further includes controlling chip layout features within the manufacturing assurance halo to ensure that manufacturing of conductive features inside the boundary of the dynamic array section is not adversely affected by chip layout features within the manufacturing assurance halo.

Methods for Defining Dynamic Array Section with Manufacturing Assurance Halo and Apparatus Implementing the Same

First and second virtual grates are defined as respective sets of parallel virtual lines extending across a layout area in first and second perpendicular directions, respectively. The virtual lines of the first and second virtual grates correspond to placement locations for layout features in lower and higher chip levels, respectively. Each intersection point between virtual lines of the first and second virtual grates is a gridpoint within a vertical connection placement grid. Vertical connection structures are placed at a number of gridpoints within the vertical connection placement grid so as to provide electrical connectivity between layout features in the lower and higher chip levels. The vertical connection structures are placed so as to minimize a number of different spacing sizes between neighboring vertical connection structures across the vertical connection placement grid, while simultaneously minimizing to an extent possible layout area size. The vertical connection structures may be contacts or vias.

Methods for defining contact grid in dynamic array architecture

A cell circuit and corresponding layout is disclosed to include linear-shaped diffusion fins defined to extend over a substrate in a first direction so as to extend parallel to each other. Each of the linear-shaped diffusion fins is defined to project upward from the substrate along their extent in the first direction. A number of gate level structures are defined to extend in a conformal manner over some of the number of linear-shaped diffusion fins. Portions of each gate level structure that extend over any of the linear-shaped diffusion fins extend in a second direction that is substantially perpendicular to the first direction. Portions of each gate level structure that extend over any of the linear-shaped diffusion fins form gate electrodes of a corresponding transistor. The diffusion fins and gate level structures can be placed in accordance with a diffusion fin virtual grate and a gate level virtual grate, respectively.

Cell circuit and layout with linear finfet structures

PROBLEM TO BE SOLVED: To provide a method for efficiently inspect a defect of a photomask after OPC correction. SOLUTION: This is a photomask pattern defect inspecting method for detecting a defect part of a photomask by comparing the pattern of a photomask with mask drawing data by a specific inspecting machine; and figure pattern data as drawing data and figure pattern data arrangement information as drawing position information of the figure pattern data are included and the figure pattern data as the drawing data are processed by the OPC correction. The photomask is inspected according to the mask drawing data to previously extract a fine figure pattern, such as a TEG pattern (test structure) of a part other than the OPC-corrected part as a fine figure pattern which should not be detected originally as a defective part, but is frequently detected as a defect part and when the photomask is inspected, the fine figure pattern part which should not be detected as a defect part originally is not regarded as a defect. COPYRIGHT: (C)2002,JPO

Photomask pattern defect inspecting method and detecting method for fine figure pattern

PROBLEM TO BE SOLVED: To provide: a generation method of pattern data for electron beam drawing, which can draw an excellent minute pattern without using a trial-and-error method by test drawing, in drawing a minute pattern using an electron beam drawing device; a proximity effect correction method used for it; and a pattern formation method using the data. SOLUTION: The generation method of pattern data for electron beam drawing is characterized in that: an energy irradiation pattern of an electron beam and an energy threshold determination pattern are generated from design pattern data; a correction value of a proximity effect is allocated to the energy irradiation pattern; a stored energy distribution when drawn by the energy irradiation pattern is calculated; a resist development threshold energy level line is extracted from the stored energy distribution based on previously-obtained resist development threshold energy; the difference between edges of the resist development threshold energy level line and the energy threshold determination pattern is calculated; and the energy irradiation pattern is output as pattern data for electron beam drawing when the difference is not larger than a predetermined determination value. COPYRIGHT: (C)2010,JPO&INPIT

Generation method of pattern data for electron beam drawing, proximity effect correction method used for the same, and pattern formation method using the data

PROBLEM TO BE SOLVED: To provide a method for determining a photomask defect for improving the production yield of photomasks and suppressing the cost of an inspection. SOLUTION: A circuit data 1 where data of a circuit to be fabricated on a semiconductor substrate by photolithography is prepared, and a layout data 2 according to the circuit data is prepared. The layout data 2 is converted into a compensated layout data 3 by using RET (resolution enhancement technology). Attribute information is imparted to each pattern in a mask production data 4, the attribute information relating to whether the pattern corresponds to an active region where an electrically active region is to be formed, or corresponds to a nonactive region where an electrically nonactive region is to be formed upon fabricating on the semiconductor substrate by photolithography. Upon determining whether the pattern formed on the photomask has a defect in an inspection step 6, the defect determination reference is varied according to the attribute information. COPYRIGHT: (C)2009,JPO&INPIT

Method for determining photomask defect

PROBLEM TO BE SOLVED: To provide a defect inspecting method for a photomask with an additional figure which has good inspection efficiency. SOLUTION: The method includes (a) a defect inspection step for detecting a defective part by inspecting the manufactured photomask with the additional figure with specific detection sensitivity by using photomask pattern data for additional figure added photomask production and then obtaining position coordinates of respective defects, (b) a discrimination data preparation step for preparing discrimination data for discriminating whether or not each detected defect is in an additional figure presence areas by arranging the discrimination data as a photomask image, (c) a defect presence area discrimination step for discriminating whether each defect is in the additional figure presence area by matching the position coordinates of the respective defects detected at the defect inspection step against the discrimination data prepared at the discrimination data preparation step, and (d) a decision step for deciding the discriminated defects with respective specifications. COPYRIGHT: (C)2003,JPO

Defect inspecting method for photomask with additional figure

PROBLEM TO BE SOLVED: To provide a drawing method and a rectangular region dividing method in electron beam drawing capable of preventing generation of a non-drawing portion and preventing occurrence of problems such as drawing irregularity or formation of stripes in the entire drawn image and degradation in LER (line edge roughness). SOLUTION: The electron beam drawing with a spot beam comprises drawing an object drawing region while irradiating and scanning the object drawing region with a spot beam, wherein a part of the scan pitch of the spot beam is irradiated with a pitch narrower than the preliminarily determined scan pitch to form an overlapped drawing portion. COPYRIGHT: (C)2008,JPO&INPIT

Terusato Narukawa

Papers

Photomask pattern defect inspecting method and detecting method for fine figure pattern

Generation method of pattern data for electron beam drawing, proximity effect correction method used for the same, and pattern formation method using the data

Method for determining photomask defect

Defect inspecting method for photomask with additional figure

Drawing method and rectangular region dividing method in electron beam drawing