A vertical depletion mode power field effect transistor having a greatly increased drain-to-source breakdown voltage. The drain region is formed in the substrate and separated from the channel by a first insulative layer having apertures which allow the passage of electrical currents. The channel, which is formed between the first insulative layer and a second insulative layer parallel to the substrate surface, contains both a source region, formed by implantation of impurities of the same type as are used to form the drain region, and a gate region. In this configuration, the normally high voltage which exists between the gate and drain is imposed over a greater distance than in conventional depletion mode vertical FETs, so that this new configuration produces vertical power FETs having much higher breakdown voltages than do conventional depletion mode vertical FETs. Islands having a conductivity type opposite to that used to form the source region are formed immediately below the second insulative layer and serve to prevent the creation of a charge inversion layer in the channel, where the inversion layer adversely affects the turn off characteristic of the j-MOS power transistor.

High voltage depletion mode MOS power field effect transistor

An insulated gate field effect transistor of the depletion mode type has a recessed gate structure with opposed gate sections on opposite sides of adjacent bar-like structures defined in a channel region. An opposite conductivity-type island in the channel region is electrically connected to the transistor gate electrode. A voltage applied to the gate electrode generates an electric field effect which extends from the opposed gate sections into said bar-like structures creating opposed depletion regions which modulate channel current. The gate voltage simultaneously biases the island to enhance the gate electric field effect by removing minority charge carriers which would otherwise accumulate in the bar-like structures.

Recessed-gate junction-MOS field effect transistor

An integrated circuit device comprises a layer of semiconductor material on an insulating substrate. At least two spaced-apart circuit components, such as field-effect transistors, are formed in the layer of semiconductor material. The circuit components are electrically isolated from each other by a method of (1) forming a layer of insulating material over the layer of semiconductor material and between the circuit components, (2) forming a layer of electrically conductive material over the layer of insulating material, and (3) providing bias means between the layer of conductive material and the layer of semiconductor material so as to deplete completely a region in the layer of semiconductor material opposite to the layer of conductive material and between the circuit components.

Semiconductor device and method of electrically isolating circuit components thereon

A charge coupled semiconductor element comprises a main path into which charges, as signals, are injected to be shifted therethrough, and a by-path into which the charges, as signals, are not injected the outputs of said main path and said by-path being differentially detected as a signal.

Charge coupled semiconductor element with noise cancellation

Line imaging and area imaging devices are described which employ the concept of storage and transfer of charge carriers in a semiconductor medium by the application of appropriate potentials to electrodes disposed above the medium. The devices are characterized by two arrays of electrodes, one functioning as an optical sensing array and the other as a storage and readout array. Charge carriers are collected in the medium under the metal electrodes of the sensing array in proportion to incident light. This information is rapidly transferred to the storage and readout array by sequentially biasing series of electrodes of the two arrays. The information may then be read out of the array without smearing while the sensing array continues to integrate. The structure includes means for preventing cross-coupling and maintaining transfer efficiency for small area electrodes.

Charge transfer imaging devices

A semiconductor device, for example, a deep-depletion field effection traNsistor, in which the formation of an inversion layer below an electrode provided on an insulating layer is counteracted by a rectifying contact preferably connected to said electrode, as a result of which minority charge carriers below the electrode layer are removed. As a result of this a depletion zone formed by the electrode potential in a semiconductor layer situated below the electrode can expand without hindrance to influence a current path in the semiconductor layer.

Theodorus Joannes Tulp

Papers

Deep depletion semiconductor device with surface inversion preventing means