An instruction detection system (1) (IDS) is capable of identifying the source of traffic, filtering the traffic (28) to classify it as either safe or suspect and then applying sophisticated detection techniques such as stateful pattern recognition, protocol parsing, heuristic detection or anomaly detection either singularly or in combination based on the traffic type. In a network environment, each traffic source (12) is provided with at least one IDS sensor (22-24) that is dedicated to monitoring a specific type of traffic such as RPC, HTTP, SMTP, DNS, or others. Traffic from each traffic source (12) is filtered to remove known safe traffic to improve efficiency and increase accuracy by keeping each IDS sensor (22-24) focused on a specific traffic type.

Intrusion detection in a data center environment

The present invention provides systems and methods for providing data transmission speeds at or in excess of 10 gigabits per second between one or more source devices and one or more destination devices. According to one embodiment, the system of the present invention comprises a first and second media access control (MAC) interfaces to facilitate receipt and transmission of packets over an associated set of physical interfaces. The system also contemplates a first and second field programmable gate arrays (FPGA) coupled to the MAC interfaces and an associated first and second memory structures, the first and second FPGAs are configured to perform initial processing of packets received from the first and second MAC interfaces and to schedule the transmission of packets to the first and second MAC interface for transmission to one or more destination devices. The first and second FPGAs are further operative to dispatch and retrieve packets to and from the first and second memory structures. A third FPGA, coupled to the first and second memory structures and a backplane, is operative to retrieve and dispatch packets to and from the first and second memory structures, compute appropriate destinations for packets and organize packets for transmission. The third FPGA is further operative to receive and dispatch packets to and from the backplane.

System and method for high speed packet transmission implementing dual transmit and receive pipelines

Provided is a compact inverter-integrated electric compressor which has good mountability and heat resistance reliability and enables reductions in vibration and noise. Specifically provided is an inverter-integrated electric compressor (1) in which an inverter device comprising a noise elimination filter circuit and an inverter circuit is incorporated into an inverter accommodation portion (9) provided at the outer periphery of a housing (2). The inverter accommodation portion (9) is provided at the outer periphery of the housing (2) and configured from an inverter box (10) in which the inverter circuit is accommodated and installed, and a junction box (11) which is integrally joined to the inverter box (10) and in which the components of the noise elimination filter circuit are accommodated and installed. The junction box (11) is joined to the inverter box (10) with the inner spaces thereof facing each other, and also serves as the cover of the inverter box (10). The noise elimination filter circuit and the inverter circuit are electrically connected.

Inverter-integrated electric compressor

Techniques for provisioning single or multistage networks using Ethernet Service Instances (ESIs). In one embodiment, an ESI is a logical entity or object that stores information that may be used to provision a network. An ESI may represent a logical entity that identifies a grouping of elements of a network or network device and associated attributes. Hierarchical relationships may be created between ESIs. The hierarchical relationships are used to perform packet-level processing including performing network packet encapsulations.

PROVISIONING SINGLE OR MULTISTAGE NETWORKS USING ETHERNET SERVICE INSTANCES (ESIs)

A network tap device may include a processor, a first network interface responsive to the processor a second network interface responsive to the processor, the second network interface configured to provide wireless network access, and memory accessible to the processor. The memory may include a network access rule. The processor may be operable to permit network traffic to flow between the first network interface and the second network interface based at least in part on network traffic in a network coupled to the first network interface in accordance with the network access rule.

System and method for controlling network access

A system and method is presented for a network tap having integrated circuitry therein for obtaining statistics about a communication line. The network tap also has a routing node for allowing information to be transmitted back into the communication line from an attached device without disrupting the communication traffic. The routing node coordinates the transmission of device data from an attached device to avoid data collisions with data transmissions already existing in the communication line. The routing node may be an Ethernet switch or field programmable gate array (FPGA). The integrated circuit may be a microprocessor or FPGA. The integrated circuit also controls other components of the network tap. The integrated circuit may also be programmed or upgraded to provide other functions.

Network tap with integrated circuitry

A network tap for enabling attached devices, such as an intrusion detection system, to transmit information into a communication line of the network without disrupting the network traffic on the communication line. When the attached device is an intrusion detection device, the network tap is connected to a firewall. An Ethernet switch or field programmable gate array (FPGA) is incorporated in the network tap to coordinate the transmission of device data to avoid data collisions with data transmissions already existing in the communication line. The network tap may be operated in various modes to accommodate different capabilities of attached devices. In addition, the network tap has various port configurations to allow a user to connect various attached devices through a single cable or dual cables and to connect various combinations of attached devices.

Network tap for use with multiple attached devices

A network tap for enabling attached devices, such as an intrusion detection system, to transmit information into a communication line of the network without disrupting the network traffic on the communication line. When the attached device is an intrusion detection device, the network tap is connected to a firewall. An Ethernet switch or field programmable gate array (FPGA) is incorporated in the network tap to coordinate the transmission of device data to avoid data collisions with data transmissions already existing in the communication line. The network tap may be operated in various modes to accommodate different capabilities of attached devices. In addition, the network tap has various port configurations to allow a user to connect various attached devices through a single cable or dual cables.

Thomas L. Gallatin

Papers

Network tap with integrated circuitry

Network tap for use with multiple attached devices

Network tap with interchangeable ports