Over-terminating the differential mode impedance of a differential transmission line, such as an INFINIBAND™ cable, at the receiving end, improves the differential signal integrity for typical variations in termination network impedance component (e.g., resistor) and transmission line characteristics. Eye opening of the differential signal can be made larger with reduced attenuation but increased jitter compared to under-terminating the differential mode impedance. Because the differential signal quality (larger eye opening) is improved, data can be transmitted over a longer transmission line with the same transmitter and receiver.

Improving signal integrity in differential signal systems

The present invention is directed to perform fine low-voltage control without largely increasing the circuit layout area in a low-power consumption structure. In the case of shifting a region to a low-speed mode, a system controller outputs a request signal and an enable signal to a power switch controller and a low-power drive circuit, respectively, to turn off a power switch and to perform a control so that the voltage level of a virtual reference potential becomes about 0.2 V to about 0.3V. The region operates on voltages between a power supply voltage and a virtual reference potential, so that it is controlled in the low-speed mode.

Semiconductor Integrated Circuit Device

In a telecommunication system (figure 1) having multiple timing subsystems (14, 16 and 18) receiving and distributing redundant timing signals, there is provided a circuitry for aligning first and second redundant timing signals (CLOCK A and CLOCK B) and switching therebetween. The circuitry includes a selecting and switching circuitry for receiving the first and second redundant timing signals (CLOCK A and CLOCK B) and designating one of the redundant timing signals as ACTIVE and the other as INACTIVE, and providing the ACTIVE timing signal as an output timing reference signal. The selecting and switching circuitry further switching the ACTIVE and INACTIVE timing signal designation and output timing reference signal in response to detecting fault or a clock switching command. The ACTIVE timing signal is provided to a first delay path (DELAY PATH A) having a programmable delay value, which delays it and produces a first output timing signal. A second delay path (DELAY PATH B) receives the INACTIVE redundant timing signal and produces a second output timing signal. The circuitry further includes a phase detector (50) which receives the ACTIVE and INACTIVE output timing signals and generates a status signal indicative of the phase relationship therebetween.

Apparatus and method for clock alignment and switching

The invention relates to a method and a device for transmission with reduced crosstalk in interconnections used for sending a plurality of signals, such as the interconnections made with flat multiconductor cables, or with the tracks of a printed circuit board, or inside an integrated circuit. An interconnection with four parallel transmission conductors plus a reference conductor has each of its ends connected to a termination circuit. The transmitting circuit receives at its input the signals of the four channels of the source and its output terminals are connected to the conductors of the interconnection. The receiving circuit's input terminals are connected to the conductors of the interconnection, and its four output channels are connected to the destination. The signals of the four channels of the source are sent to the four channels of the destination, without noticeable crosstalk.

Method and device for transmission with reduced crosstalk

Multiple controllers connected in parallel to control external circuits such as dc-dc converters so that the external circuits supply power equally to a load such as a microprocessor. All of the controllers are connected and each controller includes an oscillator and a pulse width modulation circuit to synchronize the frequency of all of the oscillators such that the duty cycle of all the oscillators are equal. Each controller includes an over-current protection circuit and an over-voltage protection circuit which will cause the controller with a fault to discontinue supplying power to the load. Each controller further includes a circuit to adjust the duty cycle of the non-faulty controllers when a controller with a fault is caused to discontinue supplying power to the load.

Synchronous current sharing pulse width modulator

A system of terminating a differential transmission line is described, where the differential transmitter and differential receiver are supplied by different power sources. The termination circuit comprises an unbalanced voltage divider pair, a connection to the receiver's voltage source, an adjustable threshold voltage, and circuitry to reduce power consumption. An unbalanced voltage divider pair provides matched termination impedances, and prevents undesired receiver output upon loss of transmitter signals. The voltage supplying the unbalanced voltage divider pair provides a voltage differential at the receiver inputs upon loss of the transmitter power source. An adjustable threshold voltage provides the minimum receiver input threshold voltage on which the transmitter signals can be superimposed. Power consumption is reduced through the use of a current limiter, which is coupled with a high pass filter to maintain the characteristic impedance of the transmission line during high frequency transmission. SEP

Differential termination network for differential transmitters and receivers

A fault tolerant multiple phase clock distribution system for providing synchronized clock signals to multiple circuit loads. Multiple electrically isolated power domains are powered by redundant AC and DC power sourcing circuits to ensure continued operation upon partial failure of the AC or DC power sourcing circuits. Multiple oscillators from the multiple power domains are synchronized to produce a group of simultaneously synchronized clock signals. Multiple synchronized clock signals from this group are then selected by selection circuitry and selection control circuitry, and are distributed to multiple circuit loads requiring simultaneous synchronization. The oscillator circuitry, synchronization circuitry, selection circuitry, and distribution circuitry is all provided in redundant form, so that the partial failure of any of the circuitry will not result in a system stop. Error recovery circuitry monitors for proper synchronization of the synchronized clock signals, and provides for automatic or manual error recovery upon detection of a synchronization error. A single phase synchronized clock signal is generated to minimize synchronization complexities, and circuitry exists at the circuit loads to generate multiple phase enable signals to emulate a multiple phase clock.

Fault tolerant clock distribution system

A redundant clock signal generator which allows the use of differing quantities of oscillators, depending on the degree of reliability desired. Synchronizers accompany each oscillator, and phase detectors monitor the phase deviation between any two oscillators in which synchronization is desired. Multiple pairs of oscillators are synchronized to produce a group of simultaneously synchronized clock signals, which are all concurrently available. Selection circuitry selects a predetermined number of the synchronized clock signals at the request of the selection control circuitry. The selection control circuitry determines which of the synchronized clock signals are to be selected either automatically or through manual intervention. Automatic selection can be triggered upon notification to the selection control circuitry of an error condition. The redundant nature of the invention allows redundant circuit loads to be clocked simultaneously, while providing redundancy in the clock signals themselves by selecting a different synchronized clock signal upon the failure of the currently active synchronized clock signal.

Redundant synchronized clock controller

A phase detecting system is provided for detecting when phase differences which occur between first and second clock pulses from a clock generator exceed acceptable tolerances, regardless of whether the first clock pulse leads the second clock pulse or the second clock pulse leads the first clock pulse. Two identical phase detectors are utilized each of which includes a phase detecting circuit, one group of signal delay elements that allow flip-flops in the phase detecting circuits time to set in order to detect the phase changes, and another group of signal delay elements coupled to the flip-flops which are set so the phase detecting circuit is capable of detecting the nominal phase delay times between the first and second clock pulses. The phase detecting circuits also each have a pair of setable latches and logic circuitry which is coupled to the latches to control them such that each latch is associated with one of the clock pulses, and the phase detecting circuits function to active clock phase identification signals that identify which of the two clock pulses leads the other.

Clock phase detecting system for detecting the phase difference between two clock phases regardless of which of the two clock phases leads the other

A glitch free clock switching circuit which produces a predictable and specifiable number of clock pulses to the system elements when switching between clock signals, even during full operation. In addition, the present invention has the capability of only switching between clocks at times that coincides with every Nth clock cycle. This is important in various types of computers systems including high reliability systems because it results in a clock switching circuit which can provide a clock signal which remains consistent throughout the computer system even in light of multiple hardware failures.

Glitch free clock start/stop control circuit for outputting a single clock signal and a single sync signal from a plurality of sync signal inputs and a plurality of clock signal inputs

Thomas T. Kubista

Papers

Differential termination network for differential transmitters and receivers

Fault tolerant clock distribution system

Redundant synchronized clock controller

Clock phase detecting system for detecting the phase difference between two clock phases regardless of which of the two clock phases leads the other

Glitch free clock start/stop control circuit for outputting a single clock signal and a single sync signal from a plurality of sync signal inputs and a plurality of clock signal inputs