“Unpaired Image-to-Image Translation using Cycle-Consistent Adversarial Networks”の学習報告

With the down-scaling of CMOS technology, the design complexity of very large-scale integrated is increasing. Although the application of machine learning (ML) techniques in electronic design autom...

Machine Learning for Electronic Design Automation: A Survey

Person re-identification (Re-ID) usually suffers from noisy samples with background clutter and mutual occlusion, which makes it extremely difficult to distinguish different individuals across the disjoint camera views. In this paper, we propose a novel deep self-paced learning (DSPL) algorithm to alleviate this problem, in which we apply a self-paced constraint and symmetric regularization to help the relative distance metric training the deep neural network, so as to learn the stable and discriminative features for person Re-ID. Firstly, we propose a soft polynomial regularizer term which can derive the adaptive weights to samples based on both the training loss and model age. As a result, the high-confidence fidelity samples will be emphasized and the low-confidence noisy samples will be suppressed at early stage of the whole training process. Such a learning regime is naturally implemented under a self-paced learning (SPL) framework, in which samples weights are adaptively updated based on both model age and sample loss using an alternative optimization method. Secondly, we introduce a symmetric regularizer term to revise the asymmetric gradient back-propagation derived by the relative distance metric, so as to simultaneously minimize the intra-class distance and maximize the inter-class distance in each triplet unit. Finally, we build a part-based deep neural network, in which the features of different body parts are first discriminately learned in the lower convolutional layers and then fused in the higher fully connected layers. Experiments on several benchmark datasets have demonstrated the superior performance of our method as compared with the state-of-the-art approaches.

Deep Self-Paced Learning for Person Re-Identification

Machine learning (ML) provides state-of-the-art performance in many parts of computer-aided design (CAD) flows. However, deep neural networks (DNNs) are susceptible to various adversarial attacks, including data poisoning to compromise training to insert backdoors. Sensitivity to training data integrity presents a security vulnerability, especially in light of malicious insiders who want to cause targeted neural network misbehavior. In this study, we explore this threat in lithographic hotspot detection via training data poisoning, where hotspots in a layout clip can be "hidden" at inference time by including a trigger shape in the input. We show that training data poisoning attacks are feasible and stealthy, demonstrating a backdoored neural network that performs normally on clean inputs but misbehaves on inputs when a backdoor trigger is present. Furthermore, our results raise some fundamental questions about the robustness of ML-based systems in CAD.

Poisoning the (Data) well in ML-Based CAD: a case study of hiding lithographic hotspots

Lithography simulation is computationally expensive for hotspot detection. Machine learning-based hotspot detection is a promising technique to reduce the simulation overhead. However, most learning approaches rely on a large amount of training data to achieve good accuracy and generality. At the early stage of developing a new technology node, the amount of data with labeled hotspots or nonhotspots is very limited. In this paper, we propose a semisupervised hotspot detection with self-paced multitask learning paradigm, leveraging both data samples with/without labels to improve model accuracy and generality. Experimental results demonstrate that our approach can achieve 4.6%–6.5% better accuracy at the same false alarm levels than the state-of-the-art work using 10%–50% of training data.

Semisupervised Hotspot Detection With Self-Paced Multitask Learning

Lithography simulation is computationally expensive for hotspot detection. Machine learning based hotspot detection is a promising technique to reduce the simulation overhead. However, most learning approaches rely on a large amount of training data to achieve good accuracy and generality. At the early stage of developing a new technology node, the amount of data with labeled hotspots or non-hotspots is very limited. In this paper, we propose a semi-supervised hotspot detection with self-paced multi-task learning paradigm, leveraging both data samples w./w.o. labels to improve model accuracy and generality. Experimental results demonstrate that our approach can achieve 2.9--4.5% better accuracy at the same false alarm levels than the state-of-the-art work using 10%-50% of training data. The source code and trained models are released on https://github.com/qwepi/SSL.

Semi-supervised hotspot detection with self-paced multi-task learning

The effective test pattern is a crucial component for lithography process optimization such as Source Mask Optimization (SMO) and Optical Proximity Correction (OPC). The conventional parameterized test patterns cannot represent various contexts of patterns, thus sample patterns extracted from layout become an alternative option. This paper introduces a sample patterns extraction method based on the hierarchical clustering algorithm, according to the geometric characteristics. Meanwhile, an improved HLAC-based method is applied to the layout patterns at the stage of feature extraction for accurate characterization. The method can reduce the number of test patterns while maintaining high coverage of layout’s geometric features. The lithography process window is analyzed to validate the effectiveness of the patterns clustering flow. Moreover, the comparison between the spectrums of sample patterns and original layout also indicates that the proposed sampling method preserve a sufficient coverage of layout’s optical characteristics. Pattern extraction method in this paper could provide a candidate solution for fast test pattern generation with high coverage for lithography process exploration.

Sample patterns extraction from layout automatically based on hierarchical cluster algorithm for lithography process optimization

Background: As semiconductor technologies continue to shrink, optical proximity correction may not have enough space to optimize layout due to limitations from adjacent layers. Lithography friendly design (LFD) becomes a powerful tool to detect potential lithography yield killers for fabless side from 14-nm technology node and beyond. Design layout can be modified before tape-out to avoid future rework. However, huge runtime is the bottleneck of LFD.
Aim: Our paper puts forward an innovative layout decomposing algorithm to accelerate LFD at full-chip level.
Approach: The proposed projection-based high coverage fast (PBHCF) LFD layout decomposing algorithm partitions the full-chip layout as a set of unique patterns. The simulation runtime can be reduced by only simulating every unique pattern and corresponding optical interaction range in full chip. The LFD hotspots will be classified, analyzed, and repaired by pattern matching in batches for full-chip layout.
Results: The experiments compare hotspot accuracies and prediction speeds of proposed PBHCF LFD and the most commonly used accelerated algorithm, Smart LFD, for different layouts at chip level for metal 2 layer of 12-nm technology node with pure unidirectional routings. On one hand, the average accuracy of PBHCF LFD can achieve 97.07%, improving 3.4% than Smart LFD on average. On the other hand, PBHCF LFD improves the average prediction speed over regular LFD 19.51%. And the PBHCF LFD is faster than Smart LFD by 5.96%.
Conclusions: PBHCF LFD achieves higher accuracy and less runtime than Smart LFD. The verification experiments conducted on layouts at chip level show the feasibility of the proposed methodology.

Projection-based high coverage fast layout decomposing algorithm of metal layer for accelerating lithography friendly design at full chip level

Extreme ultraviolet (EUV) lithography mask defects may cause severe reflectivity deformation and phase shift in advanced nodes, especially like multilayer defects. Geometric parameter characterization is essential for mask defect compensation or repair. In this paper, we propose a machine learning framework to predict the geometric parameters of multilayer defects on EUV mask blanks. With the proposed inception modules and cycle-consistent learning techniques, the framework enables a novel way of defect characterization with high accuracy.

Tianyang Gai

Papers

Semisupervised Hotspot Detection With Self-Paced Multitask Learning

Semi-supervised hotspot detection with self-paced multi-task learning

Sample patterns extraction from layout automatically based on hierarchical cluster algorithm for lithography process optimization

Projection-based high coverage fast layout decomposing algorithm of metal layer for accelerating lithography friendly design at full chip level

EUV multilayer defect characterization via cycle-consistent learning