Motivated by emerging battery-operated applications that demand intensive computation in portable environments, techniques are investigated which reduce power consumption in CMOS digital circuits while maintaining computational throughput. Techniques for low-power operation are shown which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations. An architecturally based scaling strategy is presented which indicates that the optimum voltage is much lower than that determined by other scaling considerations. This optimum is achieved by trading increased silicon area for reduced power consumption. >

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Low-power CMOS digital design

An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

The goal of this paper is to review in brief the basic physics of single-election devices, as well as their-current and prospective applications. These devices based on the controllable transfer of single electrons between small conducting "islands", have already enabled several important scientific experiments. Several other applications of analog single-election devices in unique scientific instrumentation and metrology seem quite feasible. On the other hand, the prospect of silicon transistors being replaced by single-electron devices in integrated digital circuits faces tough challenges and remains uncertain. Nevertheless, even if this replacement does not happen, single electronics will continue to play an important role by shedding light on the fundamental size limitations of new electronic devices. Moreover, recent research in this field has generated some by-product ideas which may revolutionize random-access-memory and digital-data-storage technologies.

Single-electron devices and their applications

1-V power supply high-speed low-power digital circuit technology with 0.5-/spl mu/m multithreshold-voltage CMOS (MTCMOS) is proposed. This technology features both low-threshold voltage and high-threshold voltage MOSFET's in a single LSI. The low-threshold voltage MOSFET's enhance speed performance at a low supply voltage of 1 V or less, while the high-threshold voltage MOSFET's suppress the stand-by leakage current during the sleep period. This technology has brought about logic gate characteristics of a 1.7-ns propagation delay time and 0.3-/spl mu/W/MHz/gate power dissipation with a standard load. In addition, an MTCMOS standard cell library has been developed so that conventional CAD tools can be used to lay out low-voltage LSI's. To demonstrate MTCMOS's effectiveness, a PLL LSI based on standard cells was designed as a carrying vehicle. 18-MHz operation at 1 V was achieved using a 0.5-/spl mu/m CMOS process. >

1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS

Local mechanical stress is currently an important topic of concern in microelectronics processing. A technique that has become increasingly popular for local mechanical stress measurements is micro-Raman spectroscopy. In this paper, the theoretical background of Raman spectroscopy, with special attention to its sensitivity for mechanical stress, is discussed, and practical information is given for the application of this technique to stress measurements in silicon integrated circuits. An overview is given of some important applications of the technique, illustrated with examples from the literature: the first studies of the influence of external stress on the Si Raman modes are reviewed; the application of this technique to measure stress in silicon-on-insulator films is discussed; results of measurements of local stress in isolation structures and trenches are reviewed; and the use of micro-Raman spectroscopy to obtain more information on stress in metals, by measuring the stress in the surrounding Si substrate is explained.

https://iopscience.iop.org/article/10.1088/0268-1242/11/2/001/pdf

Micro-Raman spectroscopy to study local mechanical stress in silicon integrated circuits

A dry etching method including the steps of introducing etching and deposition gases alternately into a reaction chamber at predetermined time intervals, etching the exposed surface of an article to be etched and applying deposition to the surface film thereof alternately by making plasma generated by applying power to the etching and deposition gases introduced into the reaction chamber come in contact with the article to be etched in the reaction chamber in order to etch the surface, is characterized in that the power is applied after the passage of predetermined time from the start of the introduction of the deposition gas and before the etching gas is introduced and cut off when the introduction of the etching gas is suspended.

Dry etching by alternately etching and depositing

Starting with a brief review on the single-electron memory and its significance among various single-electron devices, this paper addresses the key issues which one inevitably encounters when one tries to achieve giga-to-tera bit memory integration. Among the issues discussed are: room-temperature operation; memory-cell architecture; sensing scheme; cell-design guideline; use of nanocrystalline silicon versus lithography; array architecture; device-to-device variations; read/write error rate; and CMOS/single-electron-memory hybrid integration and its positioning among various memory architectures.

Single-electron memory for giga-to-tera bit storage

Starting with a brief review on the single-electron memory and its significance among various single-electron devices, this paper addresses the key issues which one inevitably encounters when one tries to achieve giga-to-tera bit memory integration. Among the issues discussed are: room-temperature operation; memory-cell architecture; sensing scheme; cell-design guideline; use of nanocrystalline silicon versus lithography; array architecture; device-to-device variations; read/write error rate; and CMOS/singte-electron-memor hybrid integration and its positioning among various memory architectures.

Single-electron memory for giga-to-tera bit storage : Special issue on quantum devices and their applications

A new semi-static complementary gain cell for future low power DRAM's has been proposed and experimentally demonstrated. This gain cell consists of a write-transistor and its opposite conduction type read-transistor with a heating gate as a storage node which causes a shift in the threshold voltage. This gain cell provides a two orders of magnitude larger cell signal output and higher immunity to noise on the bitlines when compared with a conventional one-transistor DRAM cell without increasing the storage capacitance even at a supply voltage of 0.8 V. The 0.87 /spl mu/m/sup 2/ cell size is achieved by using a 0.25 /spl mu/m design rule with a polysilicon thin-film transistor built in the trench and phase shifted i-line lithography. >

A semi-static complementary gain cell technology for sub-1 V supply DRAM's

Low‐temperature electron‐cyclotron‐resonance microwave plasma etching and reactive ion etching are described for ULSI device fabrication. Highly selective anisotropic etching at a high rate, which implies dry etching without tradeoffs, is performed without changing the discharge parameters. This etching is only achieved at reduced wafer temperatures. The etching mechanism and the model are discussed based on the etching yield results obtained by the mass‐selected reactive ion beam etching experiments. The new etching system and the etching properties obtained for the low‐temperature etching are reviewed comparing those obtained in the conventional reactive ion etching and electron‐cyclotron‐resonance microwave plasma etching.

Tokuo Kure

Papers

Dry etching by alternately etching and depositing

Single-electron memory for giga-to-tera bit storage

Single-electron memory for giga-to-tera bit storage : Special issue on quantum devices and their applications

A semi-static complementary gain cell technology for sub-1 V supply DRAM's

Low‐temperature dry etching