Showing papers in "IEEE Transactions on Electron Devices in 1994"
TL;DR: In this paper, the inversion layer mobility in n-and p-channel Si MOSFETs with a wide range of substrate impurity concentrations (10/sup 15/ to 10/sup 18/ cm/sup -3/) was examined.
Abstract: This paper reports the studies of the inversion layer mobility in n- and p-channel Si MOSFET's with a wide range of substrate impurity concentrations (10/sup 15/ to 10/sup 18/ cm/sup -3/). The validity and limitations of the universal relationship between the inversion layer mobility and the effective normal field (E/sub eff/) are examined. It is found that the universality of both the electron and hole mobilities does hold up to 10/sup 18/ cm/sup -3/. The E/sub eff/ dependences of the universal curves are observed to differ between electrons and holes, particularly at lower temperatures. This result means a different influence of surface roughness scattering on the electron and hole transports. On substrates with higher impurity concentrations, the electron and hole mobilities significantly deviate from the universal curves at lower surface carrier concentrations because of Coulomb scattering by the substrate impurity. Also, the deviation caused by the charged centers at the Si/SiO/sub 2/ interface is observed in the mobility of MOSFET's degraded by Fowler-Nordheim electron injection. >
1,389 citations
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TL;DR: In this paper, a survey of 1/f noise in homogeneous semiconductor samples is presented, where a distinction is made between mobility noise and number noise, and it is shown that there always is mobility noise with an /spl alpha/ value with a magnitude in the order of 10/sup -4/.
Abstract: This survey deals with 1/f noise in homogeneous semiconductor samples. A distinction is made between mobility noise and number noise. It is shown that there always is mobility noise with an /spl alpha/ value with a magnitude in the order of 10/sup -4/. Damaging the crystal has a strong influence on /spl alpha/, /spl alpha/ may increase by orders of magnitude. Some theoretical models are briefly discussed none of them can explain all experimental results. The /spl alpha/ values of several semiconductors are given. These values can be used in calculations of 1/f noise in devices. >
840 citations
TL;DR: In this article, it has been shown that V/sub th/ fluctuation is mainly caused by the statistical fluctuation of the channel dopant number which explains about 60% of the experimental results.
Abstract: Threshold voltage fluctuation has been experimentally studied, using a newly developed test structure utilizing an 8 k-NMOSFET array. It has been experimentally shown that both V/sub th/ and the channel dopant number n/sub a/ distributions are given as the Gaussian function, and verified that the standard deviation of n/sub a/, can be expressed as the square root of the average of n/sub a/, which is consistent with statistics. In this study, it has been shown that V/sub th/ fluctuation (/spl delta/V/sub th/) is mainly caused by the statistical fluctuation of the channel dopant number which explains about 60% of the experimental results. Moreover, we discuss briefly a new scaling scenario, based on the experimental results of the channel length, the gate oxide thickness, and the channel dopant dependence of /spl delta/V/sub th/. Finally, we discuss V/sub th/ fluctuation caused by the independent statistical-variations of two different dopant atoms in the counter ion implantation process. >
577 citations
TL;DR: In this article, experimental facts about noise are presented which help us to understand the correlation between noise in a device and its reliability, and the main advantages of noise measurements are that the tests are less destructive, faster and more sensitive than DC measurements after accelerated life tests.
Abstract: Experimental facts about noise are presented which help us to understand the correlation between noise in a device and its reliability. The main advantages of noise measurements are that the tests are less destructive, faster and more sensitive than DC measurements after accelerated life tests. The following topics are addressed: 1) the kind of noise spectra in view of reliability diagnostics such as thermal noise, shot noise, the typical poor-device indicators like burst noise and generation-recombination noise and the 1/f/sup 2/ and 1/f noise; 2) why conduction noise is a quality indicator; 3) the quality of electrical contacts and vias; 4) electromigration damage; 5) the reliability in diode type devices like solar cells, laser diodes, and bipolar transistors; and 6) the series resistance in modern short channel MESFET, MODFET, and MOST devices. >
545 citations
TL;DR: In this paper, a model for silicon dioxide breakdown characterization, valid for a thickness range between 25 /spl Aring/ and 130 /spl Ring/, is presented, which provides a method for predicting dielectric lifetime for reduced power supply voltages and aggressively scaled oxide thicknesses.
Abstract: In this paper, we present a model for silicon dioxide breakdown characterization, valid for a thickness range between 25 /spl Aring/ and 130 /spl Aring/, which provides a method for predicting dielectric lifetime for reduced power supply voltages and aggressively scaled oxide thicknesses. This model, based on hole injection from the anode, accurately predicts Q/sub BD/ and t/sub BD/ behavior including a fluence in excess of 10/sup 7/ C/cm/sup 2/ at an oxide voltage of 2.4 V for a 25 /spl Aring/ oxide. Moreover, this model is a refinement of and fully complementary with the well known 1/E model, while offering the ability to predict oxide reliability for low voltages. >
530 citations
TL;DR: In this article, a critical evaluation of the performance capabilities of various wide bandgap semiconductors for high power and high frequency unipolar electronic devices is presented, and seven different figures of merit have been analyzed.
Abstract: This paper presents a critical evaluation of the performance capabilities of various wide bandgap semiconductors for high power and high frequency unipolar electronic devices. Seven different figures of merit have been analyzed. Theoretical calculations show that besides diamond and SiC, compounds like AlN, GaN, InN, and ZnO, and the intermetallics (Ga/sub x/In/sub 1-x/N, Al/sub x/In/sub 1-x/N, Al/sub x/Ga/sub 1-x/N, and (AlN)/sub x/(SiC)/sub 1-x/) offer several orders of magnitude improvement in the on-resistance and in the potential for successful operation at higher temperatures. >
473 citations
TL;DR: In this article, the important material parameters for 6H silicon carbide (6H-SiC) are extracted from the literature and implemented into the 2D device simulation programs PISCES and BREAKDOWN and into the 1-D program OSSI Simulations of 6HSiC p-n junctions show the possibility to operate corresponding devices at temperatures up to 1000 K thanks to their low reverse current densities.
Abstract: The important material parameters for 6H silicon carbide (6H-SiC) are extracted from the literature and implemented into the 2-D device simulation programs PISCES and BREAKDOWN and into the 1-D program OSSI Simulations of 6H-SiC p-n junctions show the possibility to operate corresponding devices at temperatures up to 1000 K thanks to their low reverse current densities. Comparison of a 6H-SiC 1200 V p-n/sup -/-n/sup +/ diode with a corresponding silicon (Si) diode shows the higher switching performance of the 6H-SiC diode, while the forward power loss is somewhat higher than in Si due to the higher built-in voltage of the 6H-SiC p-n junction. This disadvantage can be avoided by a 6H-SiC Schottky diode. The on-resistances of Si, 3C-SiC, and 6H-SiC vertical power MOSFET's are compared by analytical calculations. At room temperature, such SiC MOSFET's can operate up to blocking capabilities of 5000 V with an on-resistance below 0.1 /spl Omega/cm/sup 2/, while Si MOSFET's are limited to below 500 V. This is checked by calculating the characteristics of a 6H-SiC 1200 V MOSFET with PISCES. In the voltage region below 200 V, Si is superior due to its higher mobility and lower threshold voltage. Electric fields in the order of 4/spl times/10/sup 6/ V/cm occur in the gate oxide of the mentioned 6H-SiC MOSFET as well as in a field plate oxide used to passivate its planar junction. To investigate the high frequency performance of SiC devices, a heterobipolartransistor with a 6H-SiC emitter is considered. Base and collector are assumed to be out of 3C-SiC. Frequencies up to 10 GHz with a very high output power are obtained on the basis of analytical considerations. >
458 citations
TL;DR: In this article, the authors presented room-temperature operation for the first time of single-electron memory, in which one electron represents one bit of information, made possible by their new one-transistor memory configuration which has a very high charge sensitivity (conventionally, three circuit elements are needed).
Abstract: This paper presents room-temperature operation, for the first time, of single-electron memory, in which one electron represents one bit of information. This is made possible by our new one-transistor memory configuration which has a very high charge sensitivity (conventionally, three circuit elements are needed). Another new technique, which facilitates single-electron memory, is the ultra-thin (3.4 nm) poly-Si film used for the active region, in which sub-10-nm-width current channels and storage dots are naturally formed. In the fabricated poly-Si TFT's a single electron is stored (or "written") on a low-energy silicon island, and the number of stored electrons is counted (or "read") by the quantized threshold-voltage shift. Single-electron memory provides the potential for new nonvolatile RAM's, suitable for mobile computers/communicators. >
411 citations
TL;DR: In this paper, the effects of scaling down on the 1/f noise in MOS transistors are studied in the ohmic region as well as in saturation, where the contribution of the gatevoltage-dependent series resistance on the drain side plays a role in lightly doped drain mini-MOST's.
Abstract: Recent experimental studies on 1/f noise in MOS transistors are reviewed. Arguments are given for the two schools of thought on the origin of 1/f noise. The consequences of models based on carrier-number /spl Delta/N or mobility fluctuations /spl Delta//spl mu/ on the device geometry and on the bias dependence of the 1/f noise are discussed. Circuit-simulation-oriented equations for the 1/f noise are discussed. The effects of scaling down on the 1/f noise is studied in the ohmic region as well as in saturation. In the ohmic region the contribution of the series resistance often can be ignored. However, in saturation the noise of the gate-voltage-dependent series resistance on the drain side plays a role in lightly doped drain LDD mini-MOST's. Surface and bulk p-channel devices are compared and the differences between n-and p-MOST's often observed is discussed. The relation between degradation effects by hot carriers or by /spl gamma/-irradiation on the one hand and the 1/f noise on the other is considered in terms of a /spl Delta/N or /spl Delta//spl mu/. Experimental results suggest that 1/f noise in n-MOST's is dominated by /spl Delta/N while in p-MOST's the noise is due to /spl Delta//spl mu/. >
371 citations
TL;DR: In this paper, the inversion layer mobilities in n-channel MOSFET's fabricated on Si wafers with three surface orientations were investigated from the viewpoint of the universal relationship against the effective field.
Abstract: For part I see ibid., vol.41, no.12, pp.2357-62 (1994). This paper reports the studies of the inversion layer mobilities in n-channel MOSFET's fabricated on Si wafers with three surface orientations ([100], [110], and [111]) from the viewpoint of the universal relationship against the effective field, E/sub eff/(=q(N/sub dpl/+/spl eta//spl middot/N/sub s/)//spl epsi/Si). It is found that the universality does hold for the electron mobilities on [110] and [111], when the value of /spl eta/ is taken to be 1/3, different from the electron mobility on [100], where /spl eta/ is 1/2. Also, the E/sub eff/ dependence of the electron mobility is found to differ among [100], [110], and [111] surfaces. This is attributed to the differences in the E/sub eff/ dependence of the mobility limited by surface roughness scattering among the orientations. The origins of E/sub eff/ and /spl eta/ are discussed on the basis of the relaxation time approximation for a 2DEG (2-dimensional electron gas). While the surface orientation dependence of /spl eta/ in phonon scattering can be understood in terms of the subband occupation, it is found that the theoretical formulation of surface roughness scattering, used currently, needs to be refined in order to explain the differences in E/sub eff/ dependence and the value of /spl eta/ among the three orientations. >
340 citations
TL;DR: In this article, the authors measured and modeled self-heating in SOI nMOSFETs under static operating conditions and showed that the measured temperature rise agrees well with the predictions of an analytical model and is a function of the silicon thickness, buried oxide thickness, and channel-metal contact separation.
Abstract: Self-heating in SOI nMOSFET's is measured and modeled. Temperature rises in excess of 100 K are observed for SOI devices under static operating conditions. The measured temperature rise agrees well with the predictions of an analytical model and is a function of the silicon thickness, buried oxide thickness, and channel-metal contact separation. Under dynamic circuit conditions, the channel temperatures are much lower than predicted from the static power dissipation. This work provides the foundation for the extraction of device modeling parameters for dynamic operation (at constant temperature) from static device characterization data (where temperature varies widely). Self-heating does not greatly reduce the electromigration reliability of SOI circuits, but might influence SOI device design, e.g., requiring a thinner buried oxide layer for particular applications and scaled geometries. >
TL;DR: In this article, a systematic study of flicker noise in CMOS transistors from twelve different fabricators is reported under various bias conditions corresponding to the gate voltage changing from subthreshold to strong inversion, and the drain voltage varying from linear to saturation regions of operation.
Abstract: Flicker noise is the dominant noise source in silicon MOSFET's. Even though considerable amount of work has been done in investigating the noise mechanism, controversy still exists as to the noise origin. In this paper, a systematic study of flicker noise in CMOS transistors from twelve different fabricators is reported under various bias conditions corresponding to the gate voltage changing from subthreshold to strong inversion, and the drain voltage changing from linear to saturation regions of operation. The measurement temperature was varied from room temperature down to 5 K. Experimental results consistently suggest that 1/f noise in n-channel devices is dominated by carrier-density fluctuation while in p-channel devices the noise is mainly due to mobility fluctuation. >
TL;DR: In this paper, a 2.0 /spl mu/m double-poly, double-metal foundry CMOS active pixel image sensor is reported, which uses TTL compatible voltages, low noise and large dynamic range, and is useful in machine vision and smart sensor applications.
Abstract: A new CMOS active pixel image sensor is reported. The sensor uses a 2.0 /spl mu/m double-poly, double-metal foundry CMOS process and is realized as a 128/spl times/128 array of 40 /spl mu/m/spl times/40 /spl mu/m pixels. The sensor features TTL compatible voltages, low noise and large dynamic range, and will be useful in machine vision and smart sensor applications. >
IBM1
TL;DR: In this paper, the p-channel SiGe MOSFETs with SiGe channels have acceptable short-channel behavior at 0.20 /spl mu/m channel lengths and are preferable to p/sup +/ polysilicon-gate p-MOSFTs for 2.5 V operation.
Abstract: The advances in the growth of pseudomorphic silicon-germanium epitaxial layers combined with the strong need for high-speed complementary circuits have led to increased interest in silicon-based heterojunction field-effect transistors. Metal-oxide-semiconductor field-effect transistors (MOSFET's) with SiGe channels are guided by different design rules than state-of-the-art silicon MOSFET's. The selection of the transistor gate material, the optimization of the silicon-germanium channel profile, the method of threshold voltage adjustment, and the silicon-cap and gate-oxide thickness sensitivities are the critical design parameters for the p-channel SiGe MOSFET. Two-dimensional numerical modeling demonstrates that n/sup +/ polysilicon-gate SiGe p-MOSFET's have acceptable short-channel behavior at 0.20 /spl mu/m channel lengths and are preferable to p/sup +/ polysilicon-gate p-MOSFET's for 2.5 V operation. Experimental results of n/sup +/-gate modulation-doped SiGe p-MOSFET's illustrate the importance of the optimization of the SiGe-channel profile. When a graded SiGe channel is used, hole mobilities as high as 220 cm/sup 2//V.s at 300 K and 980 cm/sup 2//V.s at 82 K are obtained. >
TL;DR: In this paper, an extensive comparison of the 1/f noise and radiation response of MOS devices is presented, which suggests that process techniques developed to reduce radiation-induced hole trapping in MOS circuits and devices can be applied to reduce the low-frequency 1/(f) noise of devices.
Abstract: An extensive comparison of the 1/f noise and radiation response of MOS devices is presented. Variations in the room-temperature 1/f noise of unirradiated transistors in the linear regime of device operation correlate strongly with variations in postirradiation threshold-voltage shifts due to oxide trap charge. A simple number fluctuation model has been developed to semi-quantitatively account for this correlation. The 1/f noise of irradiated n-channel MOS transistors increases during irradiation with increasing oxide-trap charge and decreases during postirradiation positive-bias annealing with decreasing oxide-trap charge. No such correlation is found between low-frequency 1/f noise and interface-trap charge. The noise of irradiated p-channel MOS transistors also increases during irradiation, but in contrast to the n-channel response, the p-channel transistor noise magnitude increases during positive-bias annealing with decreasing oxide-trap charge. A qualitative model involving the electrostatic charging and discharging of border traps, as well as accompanying changes in trap energy, is developed to account for this difference in n- and p-channel postirradiation annealing response. The correlation between the low-frequency 1/f noise of unirradiated devices and their postirradiation oxide-trap charge suggests noise measurements can be used as a nondestructive screen of oxide trap charge related failures in discrete MOS devices and for small scale circuits in which critical transistors can be isolated. It also suggests that process techniques developed to reduce radiation-induced-hole trapping in MOS devices can be applied to reduce the low-frequency 1/f noise of MOS circuits and devices. In particular, reducing the number of oxygen vacancies and vacancy complexes in the SiO/sub 2/ can significantly reduce the 1/f noise of MOS devices both in and outside a radiation environment. >
TL;DR: In this paper, a generalized charge pumping model has been developed which extends the use of charge pumping from a study of traps at the Si-SiO/sub 2/interface to trap in the oxide.
Abstract: A generalized charge pumping model has been developed which extends the use of charge pumping from a study of traps at the Si-SiO/sub 2/ interface to a study of traps in the oxide. The analytical model, based on tunneling theory, allows the spatial distribution of near-interface oxide traps to be determined from variable frequency charge pumping data. Profiling of near-interface oxide traps in irradiated MOSFET's as well as SONOS nonvolatile memory devices is presented. >
TL;DR: In this paper, an analytical model valid near and below threshold is derived for double-gate nMOS/SOI devices, which is based on Poisson's equation, containing both the doping impurity charges and the electron concentration.
Abstract: An analytical model valid near and below threshold is derived for double-gate nMOS/SOI devices. The model is based on Poisson's equation, containing both the doping impurity charges and the electron concentration. An original assumption of the constant difference between surface and mid-film potentials is successfully introduced. The model provides explicit expressions of the threshold voltage and threshold surface potential, which may no longer be assumed to be pinned at the limit of strong inversion, and demonstrates the nearly ideal subthreshold slope of ultrathin double-gate SOI transistors. Very good agreement with numerical simulations is observed. Throughout the paper we give an insight into weak inversion mechanisms occurring in thin double-gate structures. >
TL;DR: In this article, the electrical properties of polycrystalline silicon-germanium (poly-Si/sub 1/spl minus/x/Ge/sub x/) films with germanium mole fractions up to 0.56 doped by high-dose ion implantation are presented.
Abstract: The electrical properties of polycrystalline silicon-germanium (poly-Si/sub 1/spl minus/x/Ge/sub x/) films with germanium mole fractions up to 0.56 doped by high-dose ion implantation are presented. The resistivity of heavily doped p-type (P/sup +/) poly-Si/sub 1/spl minus/x/Ge/sub x/ is much lower than that of comparably doped poly-Si, because higher levels of boron activation and higher hole mobilities are achieved in poly-Si/sub 1/spl minus/x/Ge/sub x/. The resistivity of heavily doped n-type (N/sup +/) poly-S/sub 1/spl minus/x/Ge/sub x/ is similar to that of comparably doped poly-Si for x >
TL;DR: In this article, a semi-static complementary gain cell for low power DRAM's is proposed and experimentally demonstrated, which consists of a write-transistor and its opposite conduction type read-transistors with a heating gate as a storage node which causes a shift in the threshold voltage.
Abstract: A new semi-static complementary gain cell for future low power DRAM's has been proposed and experimentally demonstrated. This gain cell consists of a write-transistor and its opposite conduction type read-transistor with a heating gate as a storage node which causes a shift in the threshold voltage. This gain cell provides a two orders of magnitude larger cell signal output and higher immunity to noise on the bitlines when compared with a conventional one-transistor DRAM cell without increasing the storage capacitance even at a supply voltage of 0.8 V. The 0.87 /spl mu/m/sup 2/ cell size is achieved by using a 0.25 /spl mu/m design rule with a polysilicon thin-film transistor built in the trench and phase shifted i-line lithography. >
TL;DR: In this paper, the relationship between sheet resistance and line width is characterized by three distinct regions according to the value of W. The abrupt increase in sheet resistance observed in the region W/spl les/0.2 /spl mu/m cannot be explained in terms of the phase transition from C54 to C49, which is the cause of the rising resistance at larger W.
Abstract: The sheet resistance of TiSi/sub 2/-polycide (TiSi/sub 2/-polysilicon) lines increases as they are made narrower. This phenomenon has been investigated in detail. It is found that the relationship between sheet resistance and line width (W) is characterized by three distinct regions according to the value of W. The abrupt increase in sheet resistance observed in the region W/spl les/0.2 /spl mu/m cannot be explained in terms of the phase transition from C54 to C49, which we show to be the cause of the rising resistance at larger W. By adopting a new test pattern for sheet resistance measurements and using it in combination with TEM and EDX analysis we conclude that the cause of this abrupt increase is the presence of large inter-grain layers where silicide is very sparse. On the contrary, NiSi films have no such inter-grain layers, and good resistance values can be obtained even with 0.1 /spl mu/m lines. The NiSi process appears to be a suitable candidate to replace TiSi/sub 2/ in future deep-sub-micron high-speed CMOS devices. >
TL;DR: In this article, a model has been developed relating wearout to breakdown in thin oxides, and the average trap density immediately prior to breakdown was measured to be of the order of low-10/sup 19/cm/sup 3/ in 10 nm thick oxides fabricated on p-type substrates stressed with negative gate voltages.
Abstract: A model has been developed relating wearout to breakdown in thin oxides. Wearout has been described in terms of trap generation inside of the oxide during high voltage stressing prior to breakdown. Breakdown occurred locally when the local density of traps exceeded a critical value and the product of the electric field and the higher leakage currents through the traps exceeded a critical energy density. The measurement techniques needed for determining the density of high-voltage stress generated traps have been described along with the method for coupling the wearout measurements to breakdown distributions. The average trap density immediately prior to breakdown was measured to be of the order of low-10/sup 19//cm/sup 3/ in 10 nm thick oxides fabricated on p-type substrates stressed with negative gate voltages. The model has been used to describe several effects observed during measurements of time-dependent-dielectric-breakdown distributions. The area dependence of breakdown distributions, the differences in the breakdown distributions during constant current and constant voltage stressing, and the multi-modal distributions often observed were simulated using the model. The model contained the provision for incorporation of weak spots in the oxide. >
TL;DR: In this article, the impact of device scaling on modern MOS technology is discussed in terms of the random telegraph signals and 1/f noise in MOSFET's.
Abstract: The impact of device scaling on modern MOS technology is discussed in terms of the random telegraph signals and 1/f noise in MOSFET's. In addition to the more obvious effects of enhanced current fluctuations as the device is scaled down, we will show the influence of nonuniform distribution of threshold voltages along the channel in the context of device scaling. The role of fast interface states on the drain current fluctuations is also discussed. It will be shown that, compared to the oxide traps, fast interface states give rise to higher frequency RTS and 1/f noise, and that they become more important for devices operating in weak inversion. >
TL;DR: In this article, the 1/f noise of 3/spl mu/m/spl times/16 /spl m/m, n- and p-MOS transistors as a function of frequency (f), gatevoltage (V/sub g/) and temperature (T) were examined.
Abstract: We have examined the 1/f noise of 3 /spl mu/m/spl times/16 /spl mu/m, n- and p-MOS transistors as a function of frequency (f), gate-voltage (V/sub g/) and temperature (T) Measurements were performed for 3 Hz/spl les/f/spl les/50 kHz, 100 mV/spl les/|V/sub g/-V/sub th/|/spl les/4 V, and 77 K/spl les/T/spl les/300 K, where V/sub th/ is the threshold voltage Devices were operated in strong inversion in their linear regimes At room temperature we find that, for n-MOS transistors, S(V/sub d/)/spl prop/V/sub d//sup 2//(V/sub g/-V/sub th/)/sup 2/, and for p-MOS transistors, we generally find that S(V/sub d/)/spl prop/V/sub d//sup 2//(V/sub g/-V/sub th/, consistent with trends reported by others At lower temperatures, however, the results can be very different In fact, we find that the temperature dependence of the noise and the gate-voltage dependence of the noise show similar features, consistent with the idea that the noise at a given T and V/sub g/ is determined by the trap density, D/sub t/(E), at trap energies E=E(T,V/sub g/) Both the T- and V/sub g/-dependencies of the noise imply that D/sub t/(E) tends to be constant near the silicon conduction band edge, but increases as E approaches the valence band edge It is evidently these differences in D/sub t/(E) that lead to differences in the gate-voltage dependence of the noise commonly observed at room temperature for n- and p-MOS transistors >
TL;DR: In this paper, the authors used spectroscopy to identify the defect and measure its properties, and the value of the technique for many systems is described, and comparison is made with other methods of studying such defects.
Abstract: Electrical noise in excess of thermal and shot noise is caused by imperfections in the device. Its control can improve the quality of the device and its measurement can give considerable information about the nature of the defects involved. For defects with discrete energy distributions spectroscopy can be used to identify the defect and measure its properties. Excess noise has large intensity at low frequencies and several mechanisms can be identified. The value of the technique for many systems is described. Comparison is made with other methods of studying such defects. >
IBM1
TL;DR: In this paper, it was shown that even at sea level there is a significant component of the soft error rate that can be attributed to the effects of cosmic rays, and that the magnitude of the effects increases dramatically at higher altitudes.
Abstract: This paper provides conclusive evidence that cosmic rays cause soft errors in commercial dynamic RAM (DRAM) chips at ground level Cosmic-ray-induced soft errors in electronic components have long been a problem for the designers of satellites and spacecraft, but they have not generally been considered to be an important influence on memory chip soft error rate (SER) in terrestrial environments In an experiment designed to determine the effect of cosmic radiation on the SER of a sample of DRAM chips at ground level, the SER of a large number of chips was measured at various locations and altitudes around the US: near sea level in Essex Junction, VT; 200 m underground in a Kansas salt mine; at an altitude of 16 km in Boulder, CO; and at 31 km in Leadville, CO The results reported here show that even at sea level there is a significant component of the SER that can be attributed to the effects of cosmic rays, and that the magnitude of the effects increases dramatically at higher altitudes >
TL;DR: In this paper, the macroscopic expressions for noise sources are shown not specific to the hot carrier regime, though dependent on the electric field strength, and the microscopic noise source expressions, via the transition rates, give a unified view of the noise sources.
Abstract: After recalling the definition of the noise temperature, the macroscopic expressions for noise sources are shown not to be specific to the hot carrier regime, though dependent on the electric field strength. Careful modeling allows one to obtain important information on transport parameters from noise measurements. The microscopic noise source expressions, via the transition rates, give a unified view of the noise sources. In particular, it is clarified that noise sources are intercorrelated, and that there is also space correlations over lengths of a few mean free paths. Recent developments are reviewed, concerning noise modeling using direct numerical methods for solution of the Boltzmann equation. Finally, impedance field methods for modeling noise of devices are briefly evoked. >
TL;DR: In this article, random telegraph signals in the drain current of deep-submicron n-MOSFETs are investigated at low and high lateral electric fields at the gate oxide.
Abstract: Random telegraph signals (RTS) in the drain current of deep-submicron n-MOSFET's are investigated at low and high lateral electric fields. RTS are explained both by number and mobility fluctuations due to single electron trapping in the gate oxide. The role of the type of the trap (acceptor or donor), the distance of the trap from the Si-SiO/sub 2/ interface, the channel electron concentration (which is set by the gate bias) and the electron mobility (which is affected by the drain voltage) is demonstrated. The effect of capture and emission on average electron mobility is demonstrated for the first time. A simple theoretical model explains the observed effect of electron heating on electron capture. The mean capture time depends on the local velocity and the nonequilibrium temperature of channel electrons near the trap. The difference between the forward and reverse modes (source and drain exchanged) provides an estimate of the effective trap location along the channel. >
TL;DR: In this article, the feasibility of MOSFETs with a gate length below 0.1 /spl mu/m was evaluated through simulations of the electrical characteristics of several different device structures and addressing the most important issues related to the scaling down to ultra-short gate lengths.
Abstract: This work is a systematic investigation of the feasibility of MOSFET's with a gate length below 0.1 /spl mu/m. Limits imposed on the scalability of oxide thickness and supply voltage require a new scaling methodology which allows these parameters to be maintained constant. The feasibility of achieving sub-0.1 /spl mu/m MOSFETs in this way is evaluated through simulations of the electrical characteristics of several different device structures and by addressing the most important issues related to the scaling down to ultra-short gate lengths. This study forms a valuable starting point for the understanding of technological requirements for future ULSI. >
TL;DR: The output characteristics of multiple-input MOBILE's are described and it is demonstrated that both NAND and NOR operations are possible with the appropriate control voltage, implying the possibility of a variable function logic gate.
Abstract: The MOBILE is a logic gate exploiting the monostable-bistable transition of a circuit that consists of two resonant tunneling transistors connected in series. It has several advantages including multiple inputs and multiple functions. This paper describes the output characteristics of multiple-input MOBILE's and discusses their applications. For a two-input MOBILE, it is demonstrated that both NAND and NOR operations are possible with the appropriate control voltage. This implies the possibility of a variable function logic gate. Furthermore, the threshold logic operations for a weighted sum of input signals are demonstrated for a three-input MOBILE with a weight ratio of 4:2:1. The applications of MOBILE's in parallel processing architectures such as cellular automata and cellular neural networks are discussed based on the above results. Circuit simulations using a simple model of resonant tunneling transistors successfully reproduce the basic characteristics of MOBILE's, and demonstrate the usefulness of MOBILE's in such applications. >
TL;DR: In this article, a unified equation is introduced to relate the collapse instability criterion with other thermal instability criteria proposed for silicon bipolar transistors, and the effects of the thermal instability on the collapse behavior of 2-finger and 1-finger HBT's are examined.
Abstract: One undesirable phenomenon observed when AlGaAs/GaAs heterojunction bipolar transistors (HBT's) are operated under high power density is the collapse (of current gain). The collapse manifests itself by a distinct abrupt decrease of collector current in the transistor common-emitter current-voltage (I-V) characteristics. In this investigation, we study the substrate temperature dependence of the collapse. A unified equation is introduced to relate the collapse instability criterion with other thermal instability criteria proposed for silicon bipolar transistors. The effects of the thermal instability on the collapse behavior of 2-finger and 1-finger HBT's are examined. We also present a numerical model to adequately describe the collapse in multi-finger HBT's having arbitrary geometry. The I-V characteristics and regression plots of both ballasted and unballasted HBT's are compared. >