A simulation system for circuit design is disclosed. The system couples a schematic editor and simulator to allow incremental changes to a design under test without requiring prior shutdown of the simulator. The system uses a method which permits a wide range of changes to the design and provides a resulting netlist for the changed design. Changes can be made to the schematic which include changes in hierarchy, addition or deletion of components (including hierarchical components), addition or deletion of signals at any level within the design hierarchy, addition or deletion of interconnections of components at any level of hierarchy within the design, addition and deletion of interface ports for any component type, substitution of a new component for an existing one (including swapping hierarchical and behavioral descriptions), and alteration of parametric data such as device delay timing. The simulation continues to run after design changes are made. The method may be used in conjunction with hardware modeling systems.

Computer Aided Engineering

The current status of VLSI layout and directions for future research are addressed, with emphasis on the authors' own work Necessary terminology and definitions and, whenever possible, a precise formulation of the problems are provided Placement and floorplanning for both the sea-of-gates and building-block designs are examined The former emphasizes the connectivity specification, whereas the latter must also consider module shape and size Global routing based on a method of successive cuts on a chip is discussed This is a hierarchical top-down approach that is useful for both of the above designs A two-dimensional detailed routing problem and the rip-up and rerouting problem are also discussed The field of computational geometry and its application to layout-in particular, to gridless routing and compaction-are reviewed, and layout engines are considered >

Recent advances in VLSI layout

Existing FPGA-based logic emulators only use a fraction of potential communication bandwidth because they dedicate each FPGA pin (physical wire) to a single emulated signal (logical wire). Virtual wires overcome pin limitations by intelligently multiplexing each physical wire among multiple logical wires and pipelining these connections at the maximum clocking frequency of the FPGA. A virtual wire represents a connection from a logical output on one FPGA to a logical input on another FPGA. Virtual wires not only increase usable bandwidth, but also relax the absolute limits imposed on gate utilization. The resulting improvement in bandwidth reduces the need for global interconnect, allowing effective use of low dimension inter-chip connections (such as nearest-neighbor). Nearest-neighbor topologies, coupled with the ability of virtual wires to overlap communication with computation, can even improve emulation speeds. The authors present the concept of virtual wires and describe their first implementation, a 'softwire' compiler which utilizes static routing and relies on minimal hardware support. Results from compiling netlists for the 18 K gate Sparcle microprocessor and the 86 K gate Alewife Communications and Cache Controller indicate that virtual wires can increase FPGA gate utilization beyond 80 percent without a significant slowdown in emulation speed. >

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Virtual wires: overcoming pin limitations in FPGA-based logic emulators

Hardware accelerators, or special-purpose engines, have been used in computer-aided design applications for nearly 20 years. In this time, roughly 20 machines have been built and tested specifically for such purposes as simulation, design rule checking, placement, and routing. Their uses are increasing, and the machines are becoming commercially available. This survey describes not only the machines but also their problems and limitations. It also gives comparative data on speed-up techniques and performance. Examples include a simulation machine that achieves roughly a million-times speed-up over a conventional 1-MIP mainframe and a very low cost machine for design rule checking that provides a 100-times improvement. These and other examples clearly demonstrate the viability of special-purpose engines.

A Survey of Hardware Accelerators Used in Computer-Aided Design

To make shared-memory multiprocessors scalable, researchers are now exploring cache coherence protocols that do not rely on broadcast, but instead send invalidation messages to individual caches that contain stale data. The feasibility of such directory-based protocols is highly sensitive to the cache invalidation patterns that parallel programs exhibit. In this paper, we analyze the cache invalidation patterns caused by several parallel applications and investigate the effect of these patterns on a directory-based protocol. Our results are based on multiprocessor traces with 4, 8 and 16 processors. To gain insight into what the invalidation patterns would look like beyond 16 processors, we propose a classification scheme for data objects found in parallel applications and link the invalidation traffic patterns observed in the traces back to these high-level objects. Our results show that synchronization objects have very different invalidation patterns from those of other data objects. A write reference to a synchronization object usually causes invalidations in many more caches. We point out situations where restructuring the application seems appropriate to reduce the invalidation traffic, and others where hardware support is more appropriate. Our results also show that it should be possible to scale “well-written” parallel programs to a large number of processors without an explosion in invalidation traffic.

Analysis of cache invalidation patterns in multiprocessors

Three parallel algorithms for logic simulation have been developed and implemented on a general-purpose shared-memory parallel machine. The first algorithm is a synchronous version of a traditional event-driven algorithm which achieves speedups of 6 to 9 with 15 processors. The second algorithm is a synchronous unit-delay compiled-mode algorithm which achieves speedups of 10 to 13 with 15 processors. The third algorithm is totally asynchronous with no synchronization locks or barriers between processors and the problems of massive state storage and deadlock that are traditionally associated with asynchronous simulation have been eliminated. The processors work independently at their own speed on different elements and at different times. When simulating circuits with little or no feedback, the asynchronous simulation technique varies between speeds one to three times faster than the conventional event-driven algorithm using one processor and depending on the circuit, achieves 10 to 20% better utilization using 15 processors. >

Parallel logic simulation on general purpose machines

Bit maps have been used in many Design Automation (DA) algorithms such as printed circuit board (PCB) layout and integrated circuit (IC) design rule checking (DRC). The attraction of bit maps is that they provide a direct representation of two-dimensional images. The difficulty with large scale use of bit maps (e.g., for DRC on VLSI) is that the large amounts of data can consume impractical amounts of computation on sequential machines. This paper describes a processing architecture that is specifically designed to operate on bit maps. It has an inherently two-dimensional construction and has a very large parallel processing capability. Also included in this paper are descriptions of algorithms that exploit the architecture. Algorithms for routing, DRC, and bit vector manipulation are included.

A Parallel Bit Map Processor Architecture for DA Algorithms

In this paper we propose a new algorithm for optimal PLA folding based on a graph theoretic formulation. An efficient best-first search (BFS) algorithm is presented which finds a near-optimal PLA folding. The proposed algorithm first constructs the longest paths on the associated disjoint graph generated from the PLA personality matrix, and then extracts the ordered folding sets from the constructed paths. The algorithm is shown to be effective for most test cases.

A Best-First Search Algorithm for Optimal PLA Folding

In an effort to speed up simulation, a novel algorithm,, called incremental simulation evaluates the circuit components that can be affected directly or indirectly by design changes, utilizing the information generated during the previous simulation to reduce the number of component evaluations to a minimum. The authors describe the design and implementation of the incremental algorithm for logic or functional simulation, which substantially improves the run-time performance over existing simulators by using the incremental property of the hardware design process. >

Tom Blank

Papers

A Survey of Hardware Accelerators Used in Computer-Aided Design

Parallel logic simulation on general purpose machines

A Parallel Bit Map Processor Architecture for DA Algorithms

A Best-First Search Algorithm for Optimal PLA Folding

Fast functional simulation: an incremental approach