A Three Dimensional Structure (3DS) Memory (100) allows for physical separation of the memory circuits (103) and the control logic circuit (101) onto different layers (103) such that each layer may be separately optimized. One control logic circuit (101) suffices for several memory circuits (103), reducing cost. Fabrication of 3DS memory (100) involves thinning of the memory circuit (103) to less than 50 microns in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections (105) are used. The 3DS memory (100) manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.

Three dimensional structure memory

The Vertical System Integration (VSI) invention herein is a method for integration of disparate electronic, optical and MEMS technologies into a single integrated circuit die or component and wherein the individual device layers used in the VSI fabrication processes are preferably previously fabricated components intended for generic multiple application use and not necessarily limited in its use to a specific application. The VSI method of integration lowers the cost difference between lower volume custom electronic products and high volume generic use electronic products by eliminating or reducing circuit design, layout, tooling and fabrication costs.

Vertical system integration

One embodiment of the present invention concerns an integrated circuit that includes bond pads and special contact pads or points. The bond pads are for interfacing the integrated circuit as a whole with an external circuit, and are to be bonded to a package or circuit board. The bond pads are disposed on the die in a predetermined alignment such as a peripheral, grid, or lead-on-center alignment. The special contact pads are used to provide external test patterns to internal circuits and/or to externally monitor results from testing the internal circuits. The special contact pads may be advantageously located on the integrated circuit with a high degree of positional freedom. For one embodiment, the special contact pads may be disposed on the die at a location that is not in the same alignment as the bond pads. The special contact pads may be smaller than the bond pads so as not to increase the die size due to the special contact pads. The special contact points may also be used to externally program internal circuits (e.g., nonvolatile circuits) at the die or package level. The special contact points may also be used to select redundant circuits for faulty circuits.

Special contact points for accessing internal circuitry of an integrated circuit

Board level solder joint reliability performance during drop test is a critical concern to semiconductor and electronic product manufacturers. A new JEDEC standard for board level drop test of handheld electronic products was just released to specify the drop test procedure and conditions. However, there is no detailed information stated on dynamic responses of printed circuit board (PCB) and solder joints which are closely related to stress and strain of solder joints that affect the solder joint reliability, nor there is any simulation technique which provides good correlation with experimental measurements of dynamic responses of PCB and the resulting solder joint reliability during the entire drop impact process. In this paper, comprehensive dynamic responses of PCB and solder joints, e.g., acceleration, strains, and resistance, are measured and analyzed with a multichannel real-time electrical monitoring system, and simulated with a novel input acceleration (Input-G) method. The solder joint failure process, i.e. crack initiation, propagation, and opening, is well understood from the behavior of dynamic resistance. It is found experimentally and numerically that the mechanical shock causes multiple PCB bending or vibration which induces the solder joint fatigue failure. It is proven that the peeling stress of the critical solder joint is the dominant failure indicator by simulation, which correlates well with the observations and assumptions by experiment. Coincidence of cyclic change among dynamic resistance of solder joints dynamic strains of PCB, and the peeling stress of the critical solder joints indicates that the solder joint crack opens and closes when PCB bends down and up, and the critical solder joint failure is induced by cyclic peeling stress. The failure mode and location of critical solder balls predicted by modeling correlate well with experimental observation by cross-section and dye penetration test.

Advanced experimental and simulation techniques for analysis of dynamic responses during drop impact

In this paper, the modeling approaches for first-level solder interconnects in shock and drop of electronics assemblies have been developed without any assumptions of geometric-symmetry or loading symmetry. The problem involves multiple scales from macro-scale transient-dynamics of electronic assembly to micro-structural damage history of interconnects. Previous modeling approaches include, solid-to-solid sub-modeling (Zhu et. al., 2001) using a half test PCB board, shell-to-solid sub-modeling technique using a quarter-symmetry model (Ren et. al., 2003; 2004). Inclusion of model symmetry in state-of-art models saves computational time, but targets primarily symmetric mode shapes. The modeling approach proposed in this paper enables prediction of both symmetric and anti-symmetric modes, which may dominate an actual drop-event. Approaches investigated include, smeared property models, Timoshenko-beam element models, explicit sub-models, and continuum-shell models. Transient dynamic behavior of the board assemblies in free and JEDEC-drop has been measured using high-speed strain and displacement measurements. Model predictions have been correlated with experimental data.

Solder-joint reliability in electronics under shock and vibration using explicit finite-element sub-modeling

Effect of the drop impact on BGA/CSP package reliability

A BGA-type semiconductor device has a soldering bump a soldered state of which can be easily checked by visual inspection. A package has a bottom surface which faces the wiring board when the semiconductor device is mounted on the wiring board. A plurality of soldering bumps are provided on the bottom surface of the package. The soldering bumps are in a plurality of different sizes, and are located in positions where the soldering bumps are observable from outside of the package when the semiconductor device is mounted on the wiring board.

Semiconductor device having a bump which is inspected from outside and a circuit board used with such a semiconductor device

A semiconductor device includes a package having opposing surfaces, a first terminal for an outer connection supported by said package and electronic components supported by said package, and the opposing surfaces of the package having slits so that a shape of the package can be changed in a mounted state. Therefore, stress applied to soldered junctions of the first and second terminals is decreased.

Semiconductor device and semiconductor device mounting board

A semiconductor device includes a wiring board, an electronic component supported by the wiring board, a heat conduction layer provided in the wiring board so as to be in contact with the electronic component, and terminals provided on the wiring board and thermally connected to the heat conduction layer through thermal vias provided in the wiring board. Heat generated by the electronic component conducts to the terminals through the heat conduction layer and then conducts to a circuit board on which the semiconductor device is placed.

Semiconductor device having terminals for heat radiation

PROBLEM TO BE SOLVED: To provide a case structure of a portable telephone, which uses an Mg alloy allowing improvement of its corrosion resistance and high reliability. SOLUTION: The case structure of the portable telephone 2 having a printed wiring board accommodated therein includes a case 8 made of an Mg alloy and fixed by screw to the printed wiring board, a resin case 12 fixed by a screw to the wiring board for accommodating the wiring board therein by cooperating with the case 8, a plurality of first grounding springs 16 connected at their one ends to a grounding pattern of the wiring board and at the other ends to the alloy case, and a plurality of second grounding springs 18 connected at their one ends to the grounding pattern of the wiring board and at the other ends to a metallized film formed on an inner surface of the resin case. The alloy case is provided on its surface with an electrically-insulating resin coating and a metallic deposited film. COPYRIGHT: (C)2004,JPO

Toshio Kumai

Papers

Effect of the drop impact on BGA/CSP package reliability

Semiconductor device having a bump which is inspected from outside and a circuit board used with such a semiconductor device

Semiconductor device and semiconductor device mounting board

Semiconductor device having terminals for heat radiation

Case structure of portable telephone