Finite field arithmetic logic is central in the implementation of Reed-Solomon coders and in some cryptographic algorithms. There is a need for good multiplication and inversion algorithms that can be easily realized on VLSI chips. Massey and Omura [1] recently developed a new multiplication algorithm for Galois fields based on a normal basis representation. In this paper, a pipeline structure is developed to realize the Massey-Omura multiplier in the finite field GF(2m). With the simple squaring property of the normal basis representation used together with this multiplier, a pipeline architecture is also developed for computing inverse elements in GF(2m). The designs developed for the Massey-Omura multiplier and the computation of inverse elements are regular, simple, expandable, and therefore, naturally suitable for VLSI implementation.

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VLSI Architectures for Computing Multiplications and Inverses in GF(2 m )

Optimal normal bases in GF( p n )

Digit-serial architectures are best suited for systems requiring moderate sample rate and where area and power consumption are critical. This paper presents a new approach for designing digit-serial/parallel finite field multipliers. This approach combines both array-type and parallel multiplication algorithms, where the digit-level array-type algorithm minimizes the latency for one multiplication operation and the parallel architecture inside of each digit cell reduces both the cycle-time as well as the switching activities, hence power consumption. By appropriately constraining the feasible primitive polynomials, the mod p(x) operation involved in finite field multiplication can be performed in a more efficient way. As a result, the computation delay and energy consumption of one finite field multiplication using the proposed digit-serial/parallel architectures are significantly less than of those obtained by folding the parallel semi-systolic multipliers. Furthermore, their energy-delay products are reduced by a even larger percentage. Therefore, the proposed digit-serial/parallel architectures are attractive for both low-energy and high-performance applications.

Low-Energy Digit-Serial/Parallel Finite Field Multipliers

A parallel-in-parallel-out systolic array and a serial-in-serial-out systolic array are proposed for fast multiplication in finite fields GF(2/sup m/) with the standard basis representation. Both of the architectures possess features of regularity, modularity, concurrency, and unidirectional data flow. As a consequence, they have high throughput rates and are well suited to VLSI implementation with fault-tolerant design. As compared to the related multipliers presented by C.S. Yeh et al. (see IEEE Trans. Comput., vol.C-33, p.357-360, Apr. 1984), the proposed parallel implementation makes it easier to incorporate fault-tolerant design, and the proposed serial implementation requires only one control signal instead of two. >

Systolic array implementation of multipliers for finite fields GF(2/sup m/)

The finite fields GF(2m) play a central role in the implementation of BCH/Reed-Solomon coders and decoders. Also, these fields are attractive in some data encryption systems. In this paper we describe a method for designing a parallel multiplier for GF(2m) that is both speed and area efficient. The multiplier proposed is based on the conventional (or polynomial) base representation. From our multiplier we can derive the one introduced by Bartee and Schneider [9]. Their multiplier has been considered unsuitable for VLSI because of lack of modularity. Our approach shows that this multiplier is indeed modular and can also exhibit a high degree of regularity. It is thus well suited for VLSI. Compared to the best parallel design available today, our design requires, roughly, only half the number of gates and still achieves a high operational speed. The speed, size and regularity of our design depends on the irreducible polynomial used to generate the field. In the paper we derive two simple selection criteria for choosing the irreducible polynomial in order to obtain a good design. Also, we present a list of best polynomials for m≤16.

VLSI Designs for Multiplication over Finite Fields GF (2m)

Two systolic architectures are developed for performing the product–sum computation AB + C in the finite field GF(2m) of 2melements, where A, B, and C are arbitrary elements of GF(2m). The first multiplier is a serial-in, serial-out one-dimensional systolic array, while the second multiplier is a parallel-in, parallel-out two-dimensional systolic array. The first multiplier requires a smaller number of basic cells than the second multiplier. The second multiplier heeds less average time per computation than the first multiplier if a number of computations are performed consecutively. To perform single computations both multipliers require the same computational time. In both cases the architectures are simple and regular and possess the properties of concurrency and modularity. As a consequence they are well suited for use in VLSI systems.

Systolic Multipliers for Finite Fields GF(2 m )

In this correspondence, the complex integer multiplier and adder over the direct sum of two copies of finite field developed in [1] is specialized to the direct sum of the rings of integers modulo Fermat numbers. Such multiplication over the rings of integers modulo Fermat numbers can be performed by means of two integer multiplications, whereas the complex integer multiplication requires three integer multiplications. Such multiplications and additions can be used in the implementation of a discrete Fourier transform (DFT) of a sequence of complex numbers. The advantage of the present approach is that the number of multiplications needed to compute a systolic array of the DFT can be reduced substantially. The architectural designs using this approach are regular, simple, expandable and, therefore, naturally suitable for VLSI implementation.

Truong

Papers

Systolic Multipliers for Finite Fields GF(2 m )

Techniques for Computing the Discrete Fourier Transform Using the Quadratic Residue Fermat Number Systems