Showing papers by "Tsutomu Uesugi published in 1996"

Insulated gate semiconductor device and fabrication method therefor

Abstract: A vertical semiconductor device having an insulated gate structure makes use of a double-gate structure. The double-gate structure dramatically reduces the channel resistance, JFET resistance, and epitaxial resistance of the on-resistance of the power MOSFET, and implements an adequate breakdown voltage due to the effect of gate bias. In principle, a first gate and second gate having mutually facing portions are driven synchronously. This causes first and second channels to be formed in correspondence with first and second gates, and the currents flowing through these first and second channels form the on-current for this power device having a vertical structure.

Insulated gate semiconductor device and method of manufacture

Abstract: PROBLEM TO BE SOLVED: To realize a device that satisfies the request of both low on-state resistance and high break down voltage by reducing effectively the current amplifying factor of parasitic bipolar transistors without increasing the on resistance of power MOSFET transistor. SOLUTION: A power device such as a power MOSFET with high avalanche breakdown voltage is realized by burying an oxide film 230 into an element and utilizing an SOI structure positively. The lifetime of the minority carrier of the single crystal of a region 310 around a boundary on an embedded oxide film 230 is shorter than the lifetime of the minority carrier of the single crystals of other regions so that the lifetime of the minority carrier can be made far shorter than that of a general epitaxial Si layer and the hFE of the parasitic bipolar transistors can be made very low value. COPYRIGHT: (C)1997,JPO

Insulated-gate type semiconductor device and manufacturing method thereof

Abstract: PROBLEM TO BE SOLVED: To provide an insulated-gate type transistor which uses a trench gate having a low on resistance and a high reliability. SOLUTION: A layout pattern of a trench, insulating films 200a, 200b, gate electrode material layers 170a, 170b and source layers 290a, 290b, 290c which are traversed without any break or interruption is provided under a gate wiring line 220. Unlike the well-known concept the 'a groove or trench will not be formed under a gate wiring line', the trench is formed positively under the gate wiring line. Thereby, corner parts of the groove or trench can be substantially eliminated and thus such problems as in the prior art of fluctuations in the thickness and quality of the gate insulating film caused by the above corner parts can be removed. Further, since the trench gate structure is formed positively under such a gate wiring line which would be a dead space in the prior art, the channel width of the vertical transistor can be made larger than that of the prior art.

Semiconductor device, and manufacture of semiconductor device, and insulated gate type of semiconductor device, and manufacture of insulated gate type of semiconductor device

Abstract: PROBLEM TO BE SOLVED: To secure a finer and better source contact and improve reliability SOLUTION: A groove which has an oblique plane is made at a substrate, and besides two sidewalls are made, and a transistor is manufactured, making the most of these In short, since the trench processing end is decided, using the double sidewall 62, a fine trench can be made, getting over the limit of lithography, and besides it is of planar structure, so the processing by photolithography is easy Moreover, the oblique plane is preserved until trench formation, being covered with a second sidewall, and then the second sidewall is removed to expose the oblique plane, and the oblique plane is used as a source electrode 130 contact area, so the contact area increases, therefore the source contact resistance is reduced Moreover by the existence of the oblique plane, the bore of the trench is large, and the burying of a source electrode 130 is easy COPYRIGHT: (C)1997,JPO