Showing papers by "Tsutomu Uesugi published in 2004"
Patent•
05 Feb 2004TL;DR: A semiconductor device is formed by a first layer 32 composed of AlGaN, a second layer 42 composed of GaN and a gate electrode 34, a source electrode 38, and a drain electrode 28 as mentioned in this paper.
Abstract: A semiconductor device is formed by a first layer 32 composed of AlGaN, a second layer 42 composed of GaN, a gate electrode 34, a source electrode 38, and a drain electrode 28. The first layer 32 has a region 32 a formed between the gate electrode 34 and the second layer 42. A channel is formed in the vicinity of the boundary 24 of the first layer 32 and the second layer 42. The second layer 42 has p-type conductivity and is in contact with the source electrode 38. When electrons flow in the channel, the electrons collide with surrounding atoms, and holes are formed. If holes are accumulated inside the semiconductor device, the presence of the accumulated holes causes dielectric breakdown. In the semiconductor device of the invention, holes are discharged to the outside of the device thorough the second layer 42 and the source electrode 38, and accumulation of holes can be prevented.
65 citations
Patent•
08 Jan 2004
TL;DR: In this article, the authors proposed to improve the breakdown voltage of a semiconductor device having a group III nitride semiconductor by doping Mg as a p-type impurity.
Abstract: PROBLEM TO BE SOLVED: To improve the breakdown voltage of a semiconductor device having a group III nitride semiconductor. SOLUTION: The semiconductor device has a first layer 32 composed of AlGaN, a second layer 42 composed of GaN, a gate electrode 34, a source electrode 38, and a drain electrode 28. The first layer 32 has a region 32a formed between the gate electrode 34 and the second layer 42. A channel is formed in the vicinity of a boundary section 24 between the first layer 32 and the second layer 42. The second layer 42 is of p-type conductivity. Mg as a p-type impurity is doped. The second layer 42 is brought into contact with the source electrode 38. COPYRIGHT: (C)2004,JPO&NCIPI
52 citations
Patent•
24 Nov 2004
TL;DR: In this article, the authors proposed to suppress a leak current of a heterojunction type group III-V compound semiconductor when the semiconductor device was turned off, and to reduce resistance when the device is turned on.
Abstract: PROBLEM TO BE SOLVED: To suppress a leak current of a heterojunction type group III-V compound semiconductor device when the semiconductor device is turned off, and to reduce resistance when the device is turned on. SOLUTION: The group III-V compound semiconductor has a lower layer 46 of GaN, an upper layer 48 of AlGaN which has a heterojunction with the lower layer 46 and also has a band gap larger than a band gap of the lower layer 46, a source electrode 54 formed at a portion of the surface of the upper layer 48, and a gate electrode 52 formed at the other portion of the surface of the upper layer 48; and the lower layer 64 has a crystal defect high-density region 72 and a crystal defect low-density region distributed in a surface parallel to a heterojunction surface, the source electrode 54 is formed in a region opposed to the crystal defect low-density region, and the gate electrode 52 is formed in a region opposed to the crystal defect high-density region 72. COPYRIGHT: (C)2006,JPO&NCIPI
5 citations
DOI•
24 May 2004TL;DR: In this article, the authors proposed a new lOOV rated power MOSFET, called VLMOS @erfical &OCOS M-FEI, and investigated its performance under high temperature.
Abstract: In this paper, we proposed a new lOOV rated power MOSFET, called “VLMOS @erfical &OCOS M-FEI)“, and investigated characteristics of the VLMOS under high temperature. From simulation and experimental results, we verified that it overcame the “Si limit“ and had superior temperature characteristics in specific on-resistance. This means that the VLMOS is excellent for wide-temperature range operations, especially for automotive applications.