Proceedings ArticleDOI
Constraint generation for routing analog circuits
U. Choudhury,Alberto Sangiovanni-Vincentelli +1 more
- pp 561-566
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TLDR
It is hoped that the constraint-based approach suggested in this paper, if applied to both placement and routing, will reduce the need of time consuming layout-extraction-simulation iterations in the physical design phase of analog circuits.Abstract:
An approach for generating constraints on interconnect parasitics to drive the routing of analog circuits is presented. The approach involves (a) generation of a set of bounding constraints on the critical parasitics of a circuit to provide maximum flexibility to the router while meeting the performance constraints, and (b) deriving a set of matching constraints on the parasitics from matched-node-pair and matched-branch-pair information on differential circuits. A prototype constraint generator is described. It is hoped that the constraint-based approach suggested in this paper, if applied to both placement and routing, will reduce the need of time consuming layout-extraction-simulation iterations in the physical design phase of analog circuits. >read more
Citations
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Journal ArticleDOI
KOAN/ANAGRAM II: new tools for device-level analog placement and routing
TL;DR: KOAN and ANAGRAM II differ from previous approaches by using general algorithmic techniques to find critical device-level layout optimizations rather than relying on a large library of fixed-topology module generators.
KOAN/ANAGRAM 11: New Tools for Device-Level Analog Placement and Routing
TL;DR: In this article, the authors describe a new tool for device-level analog placement and routing called KOAN and ANAGRAM II, which uses general algorithmic techniques to find critical devicelevel layout optimizations rather than relying on a large library of fixed-topology module generators.
Book
A Top-Down, Constraint-Driven Design Methodology for Analog Integrated Circuits
Henry Chang,A. Sangiovanlli-Vincentelli,F. Balarin,Edoardo Charbon,U. Choudhury,G. Jusuf,E. Liu,E. Malavasi,R. Neff,Paul R. Gray +9 more
TL;DR: A top-down, constraint-driven design methodology for analog integrated circuits and some of the tools that support this methodology are described, including behavioral simulation tools, tools for physical assembly, and module generators.
Journal ArticleDOI
Automation of IC layout with analog constraints
TL;DR: A methodology for the automatic synthesis of full-custom IC layout with analog constraints is presented, guaranteeing that all performance constraints are met when feasible, or otherwise, infeasibility is detected as soon as possible, thus providing a robust and efficient design environment.
Proceedings ArticleDOI
Analog design automation: Where are we? Where are we going?
TL;DR: A high-level survey of the state of CAD (computer-aided design) for analog and mixed-signal ICs is presented, focusing on synthesis-related work (cell-level and system-level synthesis), with some opinions on how well the author is doing and where he appears to be heading.
References
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TL;DR: In this paper, the authors derived a related adjoint network representation and sensitivity coefficients for networks containing a very broad class of elements: those that admit a parametric representation, and a brief discussion is given as to how these results may be exploited in a general automated network design scheme.
Proceedings ArticleDOI
Automatic layout of custom analog cells in ANAGRAM
TL;DR: ANAGRAM models cell layout in the style of a macrocell place-and-route problem and circuit-simulation results based on cell extractions demonstrate the effectiveness of the crosstalk-avoidance mechanisms.
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A generalized approach to routing mixing analog and digital signal nets in a channel
R.S. Gyurcsik,J.-C. Jeen +1 more
TL;DR: A generalized algorithm for two-layer detailed channel routing of mixed analog and digital signal nets is described, which accounts for the analog routing concerns provided in the net classification table and the single-layer-only routing requirement.
Proceedings ArticleDOI
Automatic layout generation for CMOS operational amplifiers
TL;DR: An analog silicon compiler for CMOS op amps (OPASYN) has been developed and is fast enough for the program to be used interactively at the system-design level by system engineers who are inexperienced in op amp design.
Proceedings ArticleDOI
Use of performance sensitivities in routing analog circuits
TL;DR: The use of performance sensitivities in routing of analog circuits is advocated in this paper, where performance constraints are modeled in terms of the sensitivities of performance functions with respect to the routing parasitics for both single-ended and differential circuits.