Wireless systems often make use of the quadrature relationship between pairs of signals to effectively cancel out-of-band and interfering in-band signal components. The understanding of these systems is often simplified by considering both the signals and system transfer functions as "complex" quantities. The complex approach is especially useful in highly integrated multistandard receivers where the use of narrow-band fixed-coefficient filters at the RF and high IF must be minimized. This paper first presents a tutorial review of complex signal processing for wireless applications. The review emphasizes a graphical and pictorial description rather than an equation-based approach. Next, a number of classical modulation architectures are described using this formulation. Finally, more recent developments such as complex filters, image-reject mixers, low-IF receivers, and oversampling analog-digital converters are discussed.

Complex signal processing is not complex

This paper deals with the challenges in the design of millimeter-wave CMOS radios and describes circuit and architecture techniques that lead to compact, low-power transceivers. Candidate topologies for building blocks such as low-noise amplifiers, mixers, oscillators, and frequency dividers are presented. Also, a number of radio architectures that relax the generation, division, and distribution of the local oscillator signal are reviewed. Last, integration issues for transmit and receive paths and for multiple beamforming transceivers are addressed.

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Design of Millimeter-Wave CMOS Radios: A Tutorial

This paper presents a 10-Gb/s clock and data recovery (CDR) circuit for use in multichannel applications. The module aligns the phase of a plesiochronous system clock to the incoming data by use of phase interpolation. Thus, coupling between voltage-controlled oscillators (VCOs) in adjacent channels can be avoided. The controller for the phase interpolator is realized with analog circuitry to overcome the speed and phase resolution limitations of digital implementations. Fabricated in a 0.11-/spl mu/m CMOS technology the module has a size of 0.25/spl times/1.4 mm/sup 2/. The power consumption is 220 mW from a supply voltage of 1.5 V. The CDR exceeds the SDH/SONET jitter tolerance specifications with a pseudo random bit sequence of length 2/sup 23/-1 and a bit-error rate threshold of 10/sup -12/. The re-timed and demultiplexed data has an rms jitter of 3.2 ps at a data rate of 2.7 Gb/s.

A 10-gb/s CMOS clock and data recovery circuit with an analog phase interpolator

Wireless systems often make use of the quadrature relationship between pairs of signals to effectively cancel out-of-band and interfering in-band signal components. The understanding of these systems is often simplified by considering both the signals and system transfer-functions as 'complex' quantities. The complex approach is especially useful in highly-integrated multi-standard receivers where the use of narrow-band fixed-coefficient filters at the RF and high IF frequencies must be minimized. A tutorial review of complex signal processing for wireless applications emphasizing a graphical and pictorial description rather than an equation-based approach is first presented. Next, a number of classical modulation architectures are described using this formulation. Finally, more recent developments such as complex filters, image-reject mixers, low-IF receivers, and over-sampling A/D converters are discussed.

Complex signal processing is not - complex

In this tutorial paper, we present a general architecture for digital clock and data recovery (CDR) for high-speed binary links. The architecture is based on replacing the analog loop filter and voltage-controlled oscillator (VCO) in a typical analog phase-locked loop (PLL)-based CDR with digital components. We provide a linearized analysis of the bang-bang phase detector and CDR loop including the effects of decimation and self-noise. Additionally, we provide measured results from an implementation of the digital CDR system which are directly comparable to the linearized analysis, plus measurements of the limit cycle behavior which arises in these loops when incoming jitter is small. Finally, the relative advantages of analog and digital implementations of the CDR for high-speed binary links is considered

A Digital Clock and Data Recovery Architecture for Multi-Gigabit/s Binary Links

This paper presents a quadrature bandpass /spl Sigma//spl Delta/ modulator with continuous-time architecture. Due to the continuous-time architecture and the inherent anti-aliasing filter, the proposed /spl Sigma//spl Delta/ modulator needs no additional anti-aliasing filter in front of the modulator in contrast to quadrature bandpass /spl Sigma//spl Delta/ modulators with switched-capacitor architectures. The second-order /spl Sigma//spl Delta/ modulator digitizes complex analog I/Q input signals at 1-MHz intermediate frequency and operates within a clock frequency range of 25-100 MHz. The modulator chip achieves a peak signal-to-noise-distortion ratio (SNDR) of 56.7 dB and a dynamic range of 63.8 dB within a 1-MHz signal bandwidth and at a clock frequency of 100 MHz. Furthermore, it provides an image rejection of at least 40 dB. The 0.65-/spl mu/m BiCMOS chip consumes 21.8 mW at 2.7-V supply voltage.

A 1-MHz-bandwidth second-order continuous-time quadrature bandpass sigma-delta modulator for low-IF radio receivers

This paper describes a 60GHz LNA, implemented in a 65nm digital CMOS technology, that has a single-ended input and a differenntial output. At 59.3GHz, the LNA achieves a maximum voltage gain of 22.3dB (power gain of 19.3dB). The input matching is better than -lOdB over the entire 3dB bandwidth from 55.8GHz to 63.5GHz. The LNA has a minimum measured NF of 6.1dB, an output compression point of +2.7dBm and draws 29mA from a 1.2V supply.

A 22.3dB Voltage Gain 6.1dB NF 60GHz LNA in 65nm CMOS with Differential Output

Two injection-locked 2:1 frequency dividers for automotive radar applications achieve locking ranges from 82 to 94.1 GHz and from 34.3 to 42.1 GHz and consume 4mW and 8.4mW, respectively. The cascade of the two dividers can be locked from 79.7 to 81.6GHz. The 1mm2 chip is implemented in a 65nm CMOS process.

A 90GHz 65nm CMOS Injection-Locked Frequency Divider

A 10 Gb/s clock and data recovery (CDR) circuit for use in multi-channel applications is presented. The module comprises a binary phase detector, an analog phase interpolator, and a 1:4 demultiplexer. The prototype macro fabricated in a 0.11 /spl mu/m CMOS technology consumes 220 mW. The active area is about 0.25/spl times/1.4 mm/sup 2/. The CDR fulfills the jitter tolerance requirements set by SDH/SONET with the test being based on a BER of 10/sup -12/ and a PRBS of 2/sup 23/-1.

U. Langmann

Papers

A 10-gb/s CMOS clock and data recovery circuit with an analog phase interpolator

A 1-MHz-bandwidth second-order continuous-time quadrature bandpass sigma-delta modulator for low-IF radio receivers

A 22.3dB Voltage Gain 6.1dB NF 60GHz LNA in 65nm CMOS with Differential Output

A 90GHz 65nm CMOS Injection-Locked Frequency Divider

A 10-Gb/s CMOS clock and data recovery circuit with an analog phase interpolator