The invention involves the monitoring of a biological parameter through a compact analyzer. The preferred apparatus is a spectrometer based system that is attached continuously or semi-continuously to a human subject and collects spectral measurements that are used to determine a biological parameter in the sampled tissue. The preferred target analyte is glucose. The preferred analyzer is a near-IR based glucose analyzer for determining the glucose concentration in the body.

Compact apparatus for noninvasive measurement of glucose through near-infrared spectroscopy

Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device. The buffer device segments and merges the data transferred between the memory controller that expects a particular memory organization and actual memory organization.

Memory system topologies including a buffer device and an integrated circuit memory device

The invention comprises method and apparatus for fluid delivery between a sample probe and a sample. The fluid delivery system includes: a fluid reservoir, a delivery channel, a manifold or plenum, a channel or moat, a groove, and/or a dendritic pathway to deliver a thin and distributed layer of a fluid to a sample probe head and/or to a sample site. The fluid delivery system reduces sampling errors due to mechanical tissue distortion, specular reflectance, probe placement, and/or mechanically induced sample site stress/strain associated with optical sampling of the sample.

Method and apparatus for coupling a sample probe with a sample site

The invention relates generally to a probe interface method and apparatus for use in conjunction with an optical based noninvasive analyzer. More particularly, an algorithm controls a sample probe position and attitude relative to a skin sample site before and/or during sampling. For example, a sample probe head of a sample module is controlled by an algorithm along the normal-to-skin-axis. Preferably, the sample probe head is positioned in terms of 3-D location in the x-, y-, and z-axes and is attitude orientated in terms of pitch, yaw, and roll. Further, attitude of the probe head is preferably orientated prior to contact of the sample probe head with the tissue sample using indicators, such as non-contact distance feedback from capacitance sensor, contacting or non-contacting optical sensors, and/or contact electrical sensors.

Method and apparatus for controlling positioning of a noninvasive analyzer sample probe

Sampling is controlled in order to enhance analyte concentration estimation derived from noninvasive sampling. More particularly, sampling is controlled using controlled fluid delivery to a region between a tip of a sample probe and a tissue measurement site. The controlled fluid delivery enhances coverage of a skin sample site with the thin layer of fluid. Delivery of contact fluid is controlled in terms of spatial delivery, volume, thickness, distribution, temperature, and/or pressure.

Method and apparatus for coupling a channeled sample probe to tissue

A high available shared cache memory in a tightly coupled multiprocessor system provides an error self-recovery mechanism for errors in the associated cache directory or the shared cache itself. After an error in a congruence class of the cache is indicated by an error status register, self-recovery is accomplished by invalidating all the entries in the shared cache directory means of the accessed congruence class by resetting Valid bits to '0' and by setting the Parity bit to a correct value, wherein the request for data to the main memory is not cancelled. Multiple bit failures in the cached data are recovered by setting the Valid bit in the matching column to '0'. The processor reissues the request for data, which is loaded into the processor's private cache and the shared cache as well. Further requests to this data by other processors are served by the shared cache.

High available error self-recovering shared cache for multiprocessor systems

The invention concerns a multiprocessor system comprising processors PU0 to PUn and a common main memory. The memory is logically divided into at least two banks M0 and M1 and is interconnected with the processors by a bus 110. By means of control lines 111 to 118 a bus protocol is established so that one of said memory banks is accessed while another one of said banks is still busy.

Arbitration protocol for a bidirectional bus for handling access requests to a logically divided memory in a multiprocessor system

Since initiating the information technology industry-wide transition from bipolar to CMOS technology with the first generation of S/390® processors in 1994, IBM reached another major milestone with the introduction of the third generation in September 1996. The balanced system and cache structure and the modularity of the components of Generation 3 support a wide performance range from a uniprocessor to a high-performance multiprocessing system. Because of this modularity, Generation 4 is also based on this structure.

S/390 parallel enterprise server generation 3: a balanced system and cache structure

A high performance cache unit in a multiprocessing computer system comprises a shared level n cache 15 which is divided into a number of independently operated cache cores each of which containing a cache array for being used as buffer between plurality of processing units PU0-PU1 and a memory 18. Data requests and response requests issued by the processing units are separately executed in an interleaved mode to achieve a high degree of concurrency. For this purpose each cache core comprises arbitration circuits 101, 106 for an independent selection of pending data requests and response requests for execution. Selected data requests are identified by a cache directory lookup as linefetch-match or linefetch-miss operations and separately stored during their execution in operation registers 112, 114. Selected response requests are stored independently of the data requests in registers 105, 108, 109 and successively executed during free operation cycles which are not used by the execution of data requests. In this manner each of the cache cores can concurrently perform a linefetch-match operation, a linefetch-miss operation and a store operation for one processing unit or for a number of processing units.

High performance shared cache

The invention relates to a cache memory device for usage as a shared cache (3) in a multiprocessor system. The cache memory device (3) is organized in a plurality of storage blocks and has storage means (13) for storage of status information being indicative of valid or shared data of the storage blocks. The cache memory (3) further comprises logic means (15) to selectively store data in one of the storage blocks and to set the status information correspondingly.

Udo Wille

Papers

High available error self-recovering shared cache for multiprocessor systems

Arbitration protocol for a bidirectional bus for handling access requests to a logically divided memory in a multiprocessor system

S/390 parallel enterprise server generation 3: a balanced system and cache structure

High performance shared cache

Shared cache memory device