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High available error self-recovering shared cache for multiprocessor systems
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TLDR
In this article, the authors propose a self-recovery mechanism for errors in the associated cache directory or the shared cache itself by invalidating all the entries in the cache directory of the accessed congruence class by resetting Valid bits to "0" and setting the Parity bit to a correct value.Citations
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Compact apparatus for noninvasive measurement of glucose through near-infrared spectroscopy
George Acosta,James R. Henderson,N. Alan Abul Haj,Timothy L. Ruchti,Stephen L. Monfre,Thomas B. Blank,Kevin H. Hazen +6 more
TL;DR: In this article, the authors present a system that is attached continuously or semi-continuously to a human subject and collects spectral measurements that are used to determine a biological parameter in the sampled tissue.
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Method and apparatus for coupling a sample probe with a sample site
TL;DR: In this article, a fluid delivery system between a sample probe and a sample sample is described, which includes a fluid reservoir, a delivery channel, a manifold or plenum, a channel or moat, a groove, and/or a dendritic pathway.
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Method and apparatus for controlling positioning of a noninvasive analyzer sample probe
TL;DR: In this paper, a probe interface method and apparatus for use in conjunction with an optical-based non-invasive analyzer is presented, where an algorithm controls a sample probe position and attitude relative to a skin sample site before and/or during sampling.
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Method and apparatus for coupling a channeled sample probe to tissue
Thomas B. Blank,Stephen L. Monfre,Kevin H. Hazen,Timothy L. Ruchti,Christopher Slawinski,Sedar Brown +5 more
TL;DR: In this paper, a region between the tip of a sample probe and a tissue measurement site is controlled using controlled fluid delivery to enhance coverage of a skin sample site with the thin layer of fluid.
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Optical sampling interface system for in vivo measurement of tissue
Thomas B. Blank,George Acosta,Mutua Mattu,Marcy R Makarewicz,Stephen L. Monfre,Alexander D. Lorenz,Timothy L. Ruchti +6 more
TL;DR: In this paper, an optical sampling interface system minimizes and compensates error resulting from sampling variations and measurement site state fluctuations using an optical probe placement guide having an aperture wherein the optical probe is received, facilitates repeatable placement accuracy on surface of a tissue measurement site with minimal, repeatable disturbance to surface tissue.
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Patent
Shared two level cache including apparatus for maintaining storage consistency
TL;DR: In this paper, a multilevel cache buffer for a multiprocessor system is described, where each processor has a level one cache storage unit which interfaces with a level two cache unit and main storage unit shared by all processors.
Patent
Hierarchical cache arrangement wherein the replacement of an LRU entry in a second level cache is prevented when the cache entry is the only inclusive entry in the first level cache
TL;DR: In this paper, the authors present a balanced cache performance in a data processing system consisting of a first processor, a second processor, an intermediate cache memory, and a control circuit.
Patent
Error detection and correction capability for a memory system
Lawrence W Chelberg,James L King +1 more
TL;DR: In this article, the cache store includes parity generation circuits which generate check bits for the addresses to be written into a directory associated therewith, and parity check circuits for detecting errors in the addresses and information read from the cache stores during a read cycle of operation.
Patent
Method and apparatus for creating a multiprocessor verification environment
Jeffrey Kreulen,Sriram Srinivasan Mandyam,Brian O'krafka,Shahram Salamian,Ramanathan Raghavan +4 more
TL;DR: In this article, a multiprocessor test generator (MPTG) generates a set of test cases in a multi-processor test language (MTL) format subject to constraints and enumeration controls in a test specification.
Patent
Store "undo" for cache store error recovery
TL;DR: In this paper, the BPU is provided in duplicate, and all BPU data manipulation operations are performed redundantly, and the outputs from the duplicate BPUs are placed on respective master (MRB) and slave (SRB) result busses which are coupled to the cache unit where the results are compared for identity.