Repair of thin thermally grown silicon dioxide by anodic oxidation

Negative capacitance (NC) was observed in a MOS capacitor grown on an n-type substrate with ultrathin gate oxide film. The NC effect was studied by considering the oxide thickness, the lateral nonuniformity of oxide layers, the current conduction mechanism, and the minority carrier response. It was found that the NC effect turned on at the flatband voltage and was mainly attributed to local electron-hole recombination occurring at the nonuniform interface. A circuit model including an inductive pathway is proposed to take the local electron-hole recombination into account, and the estimation of the NC response on frequency approximates the experimental observation. Because the device sizes are scaled down continuously, it is important to gain an insight into the NC phenomenon induced from the nonuniform factors in fundamental MOS devices.

Comprehensive Study on Negative Capacitance Effect Observed in MOS(n) Capacitors With Ultrathin Gate Oxides

A clear current kinked phenomenon was observed in Al/SiO2/Si(p) structures with nanoscale (<2.5 nm) SiO2 in a forward biased region. It was found that the kinked points are dependent on oxide thickness and are not the same as flat-band voltages. A model regarding the oxide voltage dropping efficiency with the consideration of interface trap density (\(D_{\mathrm{it}}\)) and effective charge number density (\(Q_{\mathrm{eff}}/q\)) was proposed for the observation. It is noted that the kinked point is severely affected by the oxide quality and uniformity. However, Al/SiO2/Si(n) structures in a forward biased region do not exhibit this current kinked phenomenon because the dropping behavior of oxide is absolutely different from Al/SiO2/Si(p) structures.

Roles of interface and oxide trap density in the kinked current behavior of Al/SiO 2 /Si(p) structures with ultra-thin oxides

Study of pinholes in ultrathin SiO2 by C-AFM technique

We report a strong negative capacitance effect in back to back combination of a metal-insulator-semiconductor (MIS) structure and a metal-semiconductor junction, which is fabricated on an n type Silicon-on-Insulator substrate. The MIS capacitor comprises a SiO2-HfO2 insulator stack with embedded Pt nanoparticles. The capacitor undergoes a voltage stress process and thereby turns into a varactor and a photodetector. The negative capacitance is observed only under illumination in structures that employ a Schottky back contact. A symmetric double or an asymmetric single negative capacitance peak is observed depending on the nature of illumination. The phenomenon is attributed to the modulation of the semiconductor conductance due to photo generated carriers and their incorporation in trapping/de-trapping processes on interfacial and post filamentation induced defects in the insulator stack. The frequency range of the observed effect is limited to 100 kHz. Large ratios of light to dark and maximum to minimum ...

Negative capacitance in optically sensitive metal-insulator-semiconductor-metal structures

We have studied the effect of selective anodic oxidation on ultrathin (22-31 /spl Aring/) silicon dioxide grown at different temperatures ranging from 600/spl deg/C to 875/spl deg/C, on both p- and n-type substrates. A model based on the concept of filling of pinholes by selective anodic oxidation is presented to quantitatively explain the reduction in the gate leakage current of the MOS capacitors after selective anodic oxidation.

V.G. Marathe

Papers

A model to study the effect of selective anodic oxidation on ultrathin gate oxides