We propose a new approach to the physical design of optoelectronic system-on-a-package (SOP) using optical waveguide interconnect technology. The objective is to improve the performance of SOP by replacing long distance electrical interconnects with optical waveguide interconnects. A new simultaneous optimization algorithm for module placement and routing of electrical and optical interconnects is introduced. It not only improves the performance of SOP, but reduces the simulation time. Even though a small portion of electrical interconnects are replaced with optical interconnects, more than 21% improvement of the SOP performance is achieved.

Physical design of optoelectronic system-on-a-package: a CAD tool and algorithms

An ultra dense optical interconnection network is proposed for massively parallel processors. Using two dimensional arrays of beam steering vertical cavity surface emitting lasers (VCSEL) as space division switching elements, a single chip, free space photonic banyan network (or other multi stage networks) can be constructed. Our scheme does not require critical optical alignment and can be easily packaged in compact chips. The optical beam steering of VCSELs are realized with an integrated beam router. Steering angles as large as 10/spl deg/ from surface normal direction have been demonstrated. The VCSEL has a threshold current of 4 mA and output power of 1 mW (for 4 /spl mu/m/spl times/8 /spl mu/m device) and a modulation bandwidth of 10 GHz. Dynamic switching of optical beam angles at 2 GHz has been demonstrated.

Optical interconnection network for massively parallel processors using beam-steering vertical cavity surface-emitting lasers

A high-speed phase-locked loop for clock synchronization of optical chip-to-chip interconnects has been developed. It consists of a photo-diode, an amplifier, a phase detector, a charge pump, a loop filter, and a voltage control oscillator. In order to make our phase-locked loop operate in optical interconnects efficiently, we apply an improved fully integrated CMOS photo-detector, and propose a new phase-locked loop with a high-speed three-state phase detector and a wide-range voltage control resistor. The proposed phase-locked loop has been implemented by using the UMC 0.5 /spl mu/m CMOS technology with a die size of 300 /spl mu/m/spl times/400 /spl mu/m. The HSPICE simulation results show that the optical signals from 1.2 Gb/s (600 MHz) to 2.6 Gb/s (1.3 GHz) can be locked at a supply voltage of 3.3 V. The jitter of proposed phase-locked loop at 1 GHz is less than 15 ps. Its power consumption is around 150 mW. Therefore, our phase-locked can be widely used in high-frequency and low-power optical chip-to-chip interconnect systems.

A 3.3 V 600 MHz-1.30 GHz CMOS phase-locked loop for clock synchronization of optical chip-to-chip interconnects

In this paper, we develop a computer-aided design (CAD) tool for physical design of optoelectronic system-on-a-package (SOP) using optical waveguide interconnects. The tool assigns the optimal location to modules and replaces long electrical interconnects with optical waveguide interconnects in order to maximize the overall performance of the optoelectronic system-on-a-package. More than 47% improvement in system-on-a-package performance is obtained through the use of optical waveguide interconnects.

Physical design of optoelectronic system-on-a-package using optical waveguide interconnects

In this paper, we develop “GOETHE (Generic OptoElectronic system design THEurgist), a computer-aided design (CAD) tool for physical placement and routing in multichip modules (MCMs) manufactured using free-space optical interconnect technology. GOETHE determines the optimal module placement with the minimum propagation delay without exceeding the routing capacity of the optical substrate while reducing power consumption. More than 62% reduction in propagation delay and more than 21% reduction in power consumption is obtained through the use of freespace optical interconnect. It tiims out that chip speed can be improved by a factor of 1.5 (with less power consumption) compared to MCMs with only electrical interconnections.

https://ieeexplore.ieee.org/iel5/8632/27358/01216247.pdf

Wiring optimization for propagation delay and reduced power consumption in multichip modules with free-space optical interconnect

An introduction to current research in computer-aided design (CAD) and packaging for optoelectronic systems utilizing free space optical interconnects is presented. New CAD tools are presented that allow layout of multistage networks based on CGH fabrication limitations and the subsequent synthesis of the interconnect holograms. Recent work involving double-sided alignment of a single substrate as well as alignment techniques between two different substrates is discussed. Several packaged systems utilizing photorefractive crystals to minimize alignment problems are also presented.

V.H. Ozguz

Papers

Computer aided design and packaging optoelectronic systems with free space optical interconnects