A method and system are described to reduce process variation as a result of the semiconductor processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to modify the design and manufacture of integrated circuits.

Characterization adn reduction of variation for integrated circuits

Various methods and systems for utilizing design data in combination with inspection data are provided. One computer-implemented method for binning defects detected on a wafer includes comparing portions of design data proximate positions of the defects in design data space. The method also includes determining if the design data in the portions is at least similar based on results of the comparing step. In addition, the method includes binning the defects in groups such that the portions of the design data proximate the positions of the defects in each of the groups are at least similar. The method further includes storing results of the binning step in a storage medium.

Methods and systems for utilizing design data in combination with inspection data

Variations are characterized in feature dimensions of an integrated circuit that is to be fabricated in accordance with a design by a process that produces topographical variation in the integrated circuit, the variations in feature dimension being caused by the topographical variations. The process includes lithography or etch. Predicted characteristics are verified to conform to the design, the characteristics including feature dimensions or electrical characteristics. A process is selected for use in fabricating the integrated circuit based on the relative predicted variations. Chip-level features of a design of an integrated circuit are verified for manufacture within focus limitations of a lithographic tool. Whether a design of a level of an integrated circuit can be lithographically imaged in accordance with the design is predicted, and if it cannot be, the design or processing parameters are adjusted so that it can be.

Characterization and verification for integrated circuit designs

A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to direct the insertion of dummy fill into an integrated circuit.

Dummy fill for integrated circuits

A system for analyzing IC layouts and designs by calculating variations of a number of objects to be created on a semiconductor wafer as a result of different process conditions. The variations are analyzed to determine individual feature failures or to rank layout designs by their susceptibility to process variations. In one embodiment, the variations are represented by PV-bands having an inner edge that defines the smallest area in which an object will always print and an outer edge that defines the largest area in which an object will print under some process conditions.

Integrated circuit layout design methodology with process variation bands

Use of models in integrated circuit fabrication

Methods and systems for implementing dummy fill for integrated circuits

Chemical Mechanical Polishing (CMP) has been used in the manufacturing process for copper (Cu) damascene process.
It is well known that dishing and erosion occur during CMP process, and they strongly depend on metal density and line
width. The inherent thickness and topography variations become an increasing concern for today's designs running
through advanced process nodes (sub 65nm). Excessive thickness and topography variations can have major impacts on
chip yield and performance; as such they need to be accounted for during the design stage.
In this paper, we will demonstrate an accurate physics based CMP model and its application for CMP-related hotspot
detection. Model based checking capability is most useful to identify highly environment sensitive layouts that are prone
to early process window limitation and hence failure. Model based checking as opposed to rule based checking can
identify more accurately the weak points in a design and enable designers to provide improved layout for the areas with
highest leverage for manufacturability improvement. Further, CMP modeling has the ability to provide information on
interlevel effects such as copper puddling from underlying topography that cannot be captured in Design-for-
Manufacturing (DfM) recommended rules.
The model has been calibrated against the silicon produced with the 45nm process from Common Platform (IBMChartered-
Samsung) technology. It is one of the earliest 45nm CMP models available today. We will show that the
CMP-related hotspots can often occur around the spaces between analog macros and digital blocks in the SoC designs.
With the help of the CMP model-based prediction, the design, the dummy fill or the placement of the blocks can be
modified to improve planarity and eliminate CMP-related hotspots. The CMP model can be used to pass design
recommendations to designers to improve chip yield and performance.

Vikas Mehrotra

Papers

Characterization adn reduction of variation for integrated circuits

Dummy fill for integrated circuits

Use of models in integrated circuit fabrication

Methods and systems for implementing dummy fill for integrated circuits

Hotspot detection and design recommendation using silicon calibrated CMP model