A phased-array transmitter (TX) for multi-Gb/s non-line-of-sight links in the four frequency channels of the IEEE 802.15.3c standard (58.32 to 64.8 GHz) is fully integrated in a 0.12-μm SiGe BiCMOS process. It consists of an up-conversion core followed by a 1:16 power distribution tree, 16 phase-shifting front-ends, and a digital control unit. The TX core is a two-step sliding-IF up-conversion chain with frequency synthesizer that features 40 dB of gain programmability, I/Q balance and LO leakage correction, and a modulator for 802.15.3c common-mode signaling. The tradeoffs involved in the implementation of a 1:16 power distribution network are analyzed and a hybrid passive/active distribution tree architecture is introduced. Each of the 16 front-ends consists of a balanced passive phase shifter and a variable-gain, 3-stage PA that features oP1dB programmability through the bias control of the its final stage. All of the chip features are digitally controllable and individual memory arrays are integrated at each front-end to enable fast beam steering through a high-speed parallel interface. The IC occupies 44 mm and is fully characterized on wafer. The TX delivers 9 to 13.5 dBm oPidB per element at 60.48 GHz with a total power consumption of 3.8 to 6.2 W. Each element attains a phase-shift range >360° with an amplitude variation <;±1 dB across phase settings and adjacent elements. Measurement results from a packaged IC in an antenna chamber are also presented including the demonstration of spatial power combining up to +40 dBm EIRP and 16-element radiation patterns.

A Fully Integrated 16-Element Phased-Array Transmitter in SiGe BiCMOS for 60-GHz Communications

This paper presents a fully integrated 60GHz transceiver module in a 65nm CMOS technology for wireless high-definition video streaming. The CMOS chip is compatible with the WirelessHD™ standard, covers the four channels and supports 16-QAM OFDM signals including the analog baseband. The ESD-protected die (9.3mm²) is flip-chipped atop a High Temperature Cofired Ceramic (HTCC) substrate, which receives also an external PA and the emission and reception glass-substrate antennas. The module occupies an area of only 13.5×8.5mm². It consumes 454mW in receiver mode and 1.357W in transmitter mode (357mW for the transmitter and 1W for the PA).

A 65-nm CMOS Fully Integrated Transceiver Module for 60-GHz Wireless HD Applications

Transceiver architecture selection: Review, state-of-the-art survey and case study

This paper presents a novel approach to design a digitally programmable low pass filter (LPF) and variable gain amplifier (VGA) intended for a software-defined radio (SDR) front-end. These flexible analog circuits are driven by a network-on-chip (NoC) that is able to set performance parameters like cut-off frequency, selectivity, noise, and gain guaranteeing at any time a near-optimal power/perfomance trade-off. A design approach is proposed to tackle the challenges imposed by flexibility in analog design. A silicon prototype is realized in 0.13-μm CMOS technology with 1.2-V supply voltage to prove the validity of the proposed solution. The LPF provides a frequency tuning range between 0.35 MHz and 23.5 MHz with an adaptive integrated noise level between 85 μVrms and 163 μVrms whereby the power consumption conveniently varies from 0.72 mW to 21.6 mW according to the required performance. The VGA is made up of two cascaded gain stages and provides a gain range from about 0 dB to 39 dB with a reconfigurable power/bandwidth.

Flexible baseband analog circuits for software-defined radio front-ends

An asynchronous 6 bit 1 GS/s ADC is achieved by time interleaving two ADCs based on the binary successive approximation (SA) algorithm using a series capacitive ladder. The semi-closed loop asynchronous technique eliminates the high internal clocks and significantly speeds up the SA algorithm. A key feature to reduce the power in this design involves relaxing the comparator requirements using an error correction technique, which can be viewed as an extension of the SA algorithm to remove degradation due to metastability. Fabricated in 65 nm CMOS with an active area of 0.11 mm2, it achieves a peak SNDR of 31.5 dB at 1GS/s sampling rate and has a total power consumption of 6.7 mW.

A 1 GS/s 6 Bit 6.7 mW Successive Approximation ADC Using Asynchronous Processing

An integrated fifth-order continuous-time low-pass filter for a WiMedia ultrawideband radio receiver is described in this paper. The prototype filter is realized with a passive pole at the filter input and a fourth-order leapfrog filter in which the gm-C technique with pseudodifferential transconductors is used. The transconductors do not include internal nodes, and they are designed to have a nominal 26-dB dc gain, of which process, voltage, and temperature variations are controlled by means of a negative resistance circuit. The losses of the low-dc-gain filter integrators are already taken into account in the filter synthesis. The passband edge frequency of the implemented filter is 240 MHz in order to receive multiband-orthogonal-frequency-division-multiplexing signals using the direct-conversion topology. The voltage gain of the filter can be controlled from 9 to 43 dB in the 1-dB gain steps. The filter achieves a 7.8-nVradicHz input-referred noise density, a -8-dBV out-of-band third-order intermodulation intercept point, and a +15-dBV out-of-band second-order intermodulation intercept point. The circuit uses a 1.2-V supply and has been fabricated in a modern 65-nm CMOS technology.

A 240-MHz Low-Pass Filter With Variable Gain in 65-nm CMOS for a UWB Radio Receiver

A 240MHz 5th-order gm-C low-pass filter for WiMedia UWB system is presented. The filter uses a 1.2V supply and is fabricated in 0.13mum CMOS. The filter is targeted for a direct-conversion radio receiver and is based on precise-gain filter synthesis. It includes gain control from 13 to 48dB in 1dB steps. The filter achieves an input-referred noise of 7.7nV/radicHz, an out-of-band IIP3 of -8.2dBV and consumes 24mW

A 1.2V 240MHz CMOS Continuous-Time Low-Pass Filter for a UWB Radio Receiver

A broadband 60-GHz receiver implemented in a 65-nm baseline CMOS technology is presented. A millimeter-wave front-end, including a single-ended low noise amplifier and a balanced resistive mixer, an IF-stage and an analog baseband circuit with an analog-to-digital converter are integrated on a single chip. The receiver achieves a measured 7.0-dB noise figure at 60 GHz and the voltage gain can be controlled between 45 to 79 dB. The measured 1-dB input compression point is −38.5 dBm.

A 60-GHz CMOS receiver with an on-chip ADC

The multicarrier receiver IC described in this paper receives four adjacent WCDMA channels simultaneously in order to reduce the component count of a base-station. The receiver uses low-IF architecture and it is fabricated with a 0.25-mum SiGe BiCMOS process to meet the high-performance requirements set by the base-station application. The receiver includes a dual-input low-noise amplifier (LNA), quadrature mixers, a local-oscillator (LO) divider, IIP2 calibration circuits, 10-MHz low-pass filters, and ADC buffers. The receiver noise figures, measured over the downconverted WCDMA channels centered at 2.5-MHz and 7.5-MHz intermediate frequencies, are 3.0 dB and 2.6 dB, respectively. The receiver achieves 47-dB voltage gain and -12-dBm out-of-band IIP3 and consumes 535mW from a 2.5-V supply

WCDMA multicarrier receiver for base-station applications

An integrated two-stage class-E power amplifier operating at the 2.4 GHz frequency range is described. The implemented power amplifier is capable of providing 21.3 dBm output power with power added efficiency of 40 % and gain of 14.3 dB at 2.4 GHz. The drain efficiency of the class-E power stage is 55 % at 21.3 dBm power. The power amplifier uses 3.3 V supply voltage and was fabricated with 0.18 /spl mu/m CMOS technology. The linear gain is 23.8 dB and the chip area 0.43 mm/sup 2/.

Ville Saari

Papers

A 240-MHz Low-Pass Filter With Variable Gain in 65-nm CMOS for a UWB Radio Receiver

A 1.2V 240MHz CMOS Continuous-Time Low-Pass Filter for a UWB Radio Receiver

A 60-GHz CMOS receiver with an on-chip ADC

WCDMA multicarrier receiver for base-station applications

Integrated 2.4 GHz class-E CMOS power amplifier