Showing papers by "Vincenzo Piuri published in 1987"
18 May 1987
TL;DR: A fault-tolerant architecture is proposed to allow reliable computation of systolic arrays by using physical redundancy and residue number coding.
Abstract: Much attention has been recently given to VLSI and WSI processing arrays: systolic arrays are often adopted to execute a wide class of algorithms, e.g for matrix arithmetic or signal and image processing. In this paper a fault-tolerant architecture is proposed to allow reliable computation of systolic arrays by using physical redundancy and residue number coding. Such architecture supplies also information for fast reconfiguration.
14 citations
TL;DR: Criteria allowing the identification of the best set of bases to detect and correct a given number of bits of the considered multiplier and the results obtained are presented.
12 citations
Proceedings Article•
01 Jan 1987
7 citations
TL;DR: A heuristic algorithm for dimensioning of hardware architecture is proposed to find a configuration allowing a task allocation which minimizes costs and satisfies predefined performance constraints.
7 citations
TL;DR: This paper deals with the dimensioning of a multiprocessor system and allocation of processs minimizing hardware costs and satisfying performance and reliablity constraints: easy reconfiguration and reactivation after hardware faults are the main goals.
4 citations
TL;DR: Criteria are proposed to choose the best folding strategy among those considered, without performing all the possible foldings, to ensure accurate evaluation of the area used by folded PLA's.
2 citations