Showing papers in "Integration in 1987"

TL;DR: A new global router applicable for any object with a defined channel structure based on a multicommodity flow model in the graph form with hierarchical cost function that is proved to be NP-complete.

TL;DR: In this article, the authors describe a new global router applicable for any object with a defined channel structure, which can be used for the routing of chips and boards with rectilinear or non-rectileinear channel structures.

TL;DR: The design and architecture of an array processor for the 2-dimensional discrete cosine transform, DCT is discussed, aimed for used in high speed applications, e.g., transform coding of TV images in real time.

TL;DR: Two new algorithms that make hierarchical geometric design rule checkers more efficient are presented, a method to reduce the number of design rules to be checked when a subcell interact with layout outside the subcell and one that checks large array of cells in a very efficient way.

TL;DR: A novel technique is proposed for solving the VLSI layout problem to recursively interconnect a set of modules, in conformity with the design rules, by merging a pair of strongly-connected modules.

TL;DR: A more complex CMOS graph model is developed which includes a ternary transient analysis and is capable of handling some unconventional, but commercially used, combinational networks.

TL;DR: A heuristic algorithm for optimal PLA column folding which is both effective in finding optimal solutions and fast enough to handle large PLAs is developed.

TL;DR: The objective of this paper is to review how computational geometry is applied to the LSI layout problems such as mask pattern design verification, manipulation of mask data and image processing, wire routing, etc.

TL;DR: A VLSI design is presented for the solution of a linear system tailored to handle general sparse coefficient matrices, showing a network with area proportional to the number of nonzero entries in the matrix and modularity not dependent on the particular coefficient matrix.

TL;DR: The chip physics can be used to show the superiority of mesh algorithms over wire bound layouts such as the shuffle exchange graph, and the representation of processor arrays as a kind of supercrystal may be suggestive in developing formal methods of understanding complex systems.

TL;DR: A method to implement restricted timed Petri nets by microprograms is described, which consists of a set of transformation algorithms which have been implemented as parts of CAMAD, an integrated design aid system.

TL;DR: A low cost custom integrated circuit implementing the FIR Median Hybrid Filter is introduced, which produces results that are essentially equivalent to median filtering, however, the VLSI implementation is orders of magnitude simpler.

TL;DR: A general-purpose test stand is described, designed and built at the Santa Barbara campus of the University of California, to support functional testing and characterization of arbitrary NMOS and CMOS VLSI chips packaged with up to 40 pins.

TL;DR: Criteria are proposed to choose the best folding strategy among those considered, without performing all the possible foldings, to ensure accurate evaluation of the area used by folded PLA's.

TL;DR: This paper shows that allowing some of the pins to be interchanged can lead to a substantial reduction in the number of tracks needed for routing, and shows that the PCRP is NP-complete for two different cost measures.

TL;DR: A parallel connection machine architecture which is capable of assisting with the DRC of VLSI circuits and a significant performance improvement can be expected from this machine.

TL;DR: A simulation tool for systolic processor design has been built using synchronous communicating processes and the simulation language allows for hierarchical definition of processor cells.

TL;DR: The semantics of a hardware description language, ASL, and a set of transformation rules related to this language are presented and transformation rules treated allow transformation from an actional description to a more functional description.

TL;DR: VLSI facility is established to support ongoing studies of algorithms for multiprocessors, and can design, fabricate, and test custom VLSI components.

TL;DR: An expandable arithmetic block macrocell was designed and implemented that performs multiplication, accumulation, addition, and several logic functions and can be used in conjunction with other macrocells to custom design a full digital singal processor with varying bit resolution and storage requirements.