Showing papers by "Vivek Tiwari published in 1993"
14 Jun 1993
TL;DR: This paper focuses on the problem of mapping a technology independent circuit to a technology specific one, using gates from a given library, with power as the optimization metric, and observes that a significant variation in the power consumption is possible just by varying the choice of gates.
Abstract: The last couple of years have seen the addition of a new dimension in the evaluation of circuit quality - its power requirements. Low power circuits are emerging as an important application domain, and synthesis for low power is demanding attention. The research presented in this paper addresses one aspect of low power synthesis. It focuses on the problem of mapping a technology independent circuit to a technology specific one, using gates from a given library, with power as the optimization metric. Several issues in modeling and measuring circuit power, as well as algorithms for technology mapping for low power are presented here. Empirically, it is observed that a significant variation in the power consumption is possible just by varying the choice of gates. Technology mapping for low power provides circuits with up to 24% lower power requirements than those obtained by technology mapping for area.
140 citations
01 Jul 1993
TL;DR: This paper focuses on the problem of mapping a technology independent circuit to a technology specific one, using gates from a given library, with power as the optimization metric, and observes that a significant variation in the power consumption is possible just by varying the choice of gates.
Abstract: The last couple of years have seen the addition of a new dimension in the evaluation of circuit quality - its power requirements. Low power circuits are emerging as an important application domain, and synthesis for low power is demanding attention. The research presented in this paper addresses one aspect of low power synthesis. It focuses on the problem of mapping a technology independent circuit to a technology specific one, using gates from a given library, with power as the optimization metric. Several issues in modeling and measuring circuit power, as well as algorithms for technology mapping for low power are presented here. Empirically, it is observed that a significant variation in the power consumption is possible just by varying the choice of gates. Technology mapping for low power provides circuits with up to 24% lower power requirements than those obtained by technology mapping for area.
131 citations
03 Oct 1993
TL;DR: This paper proposes and evaluates a split data cache memory design, a new memory system ehancement for superscalar processor architectures that doubles peak bandwidth without the expense or complexity of multi-ported memory, and increases the processor's ability to exploit fine-grained parallelism.
Abstract: Superscalar implementations of RISC architectures are emerging as the dominant high-performance microprocessor technology for the mid-1990's. This paper proposes and evaluates a split data cache memory design, a new memory system ehancement for superscalar processor architectures. This design allows floating-point and integer memory access to be executed in parallel. The configuration is well matched to the dual-path execution hardware of many current superscalar processors. It doubles peak bandwidth without the expense or complexity of multi-ported memory, and increases the processor's ability to exploit fine-grained parallelism. The reported simulation results show that by using this enhancement, a speedup of more than 1.5 over the traditional unified cache model can be achieved on some standard benchmarks. The speedup is not uniform among all programs. Several hypotheses are presented and experimentally validated to explain these results. >
5 citations