Technology Mapping for Low Power
Vivek Tiwari,Pranav Ashar,Sharad Malik +2 more
- pp 74-79
TLDR
This paper focuses on the problem of mapping a technology independent circuit to a technology specific one, using gates from a given library, with power as the optimization metric, and observes that a significant variation in the power consumption is possible just by varying the choice of gates.Abstract:
The last couple of years have seen the addition of a new dimension in the evaluation of circuit quality - its power requirements. Low power circuits are emerging as an important application domain, and synthesis for low power is demanding attention. The research presented in this paper addresses one aspect of low power synthesis. It focuses on the problem of mapping a technology independent circuit to a technology specific one, using gates from a given library, with power as the optimization metric. Several issues in modeling and measuring circuit power, as well as algorithms for technology mapping for low power are presented here. Empirically, it is observed that a significant variation in the power consumption is possible just by varying the choice of gates. Technology mapping for low power provides circuits with up to 24% lower power requirements than those obtained by technology mapping for area.read more
Citations
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Journal ArticleDOI
Minimizing power consumption in digital CMOS circuits
TL;DR: An approach is presented for minimizing power consumption for digital systems implemented in CMOS which involves optimization at all levels of the design and has been applied to the design of a chipset for a portable multimedia terminal that supports pen input, speech I/O and full-motion video.
Book ChapterDOI
A Taxonomy and Survey of Energy-Efficient Data Centers and Cloud Computing Systems
Anton Beloglazov,Anton Beloglazov,Rajkumar Buyya,Rajkumar Buyya,Young Choon Lee,Young Choon Lee,Albert Y. Zomaya,Albert Y. Zomaya +7 more
TL;DR: This study discusses causes and problems of high power/energy consumption, and presents a taxonomy of energy-efficient design of computing systems covering the hardware, operating system, virtualization, and data center levels.
Journal ArticleDOI
Power minimization in IC design: principles and applications
TL;DR: An in-depth survey of CAD methodologies and techniques for designing low power digital CMOS circuits and systems is presented and the many issues facing designers at architectural, logical, and physical levels of design abstraction are described.
Proceedings ArticleDOI
Reducing power in high-performance microprocessors
TL;DR: The main trends that are driving the increased focus on design for low power are described and areas that need increased research focus in the future are also pointed out.
Journal ArticleDOI
Techniques for minimizing power dissipation in scan and combinational circuits during test application
TL;DR: Heuristics with good performance bounds can be derived for combinational circuits tested using built-in self-test (BIST) and considerable reduction in power dissipation can be obtained using the proposed techniques.
References
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Journal ArticleDOI
Graph-Based Algorithms for Boolean Function Manipulation
TL;DR: In this paper, the authors present a data structure for representing Boolean functions and an associated set of manipulation algorithms, which have time complexity proportional to the sizes of the graphs being operated on, and hence are quite efficient as long as the graphs do not grow too large.
Journal ArticleDOI
Low-power CMOS digital design
TL;DR: In this paper, techniques for low power operation are presented which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations to reduce power consumption in CMOS digital circuits while maintaining computational throughput.
Journal Article
Low-Power CMOS Digital Design
TL;DR: An architecturally based scaling strategy is presented which indicates that the optimum voltage is much lower than that determined by other scaling considerations, and is achieved by trading increased silicon area for reduced power consumption.
Book
Principles of CMOS VLSI Design: A Systems Perspective
Neil Weste,K Eshraghian +1 more
TL;DR: CMOS Circuit and Logic Design: The Complemenatry CMOS Inverter-DC Characteristics and Design Strategies.
PRINCIPLES OF CMOS VLSI DESIGN A Systems Perspective Second Edition
Neil Weste,Kamran Eshraghian +1 more
Abstract: Introduction to CMOS Circuits. Introduction. MOS Transistors. MOS Transistor Switches. CMOS Logic. Circuit Representations. CMOS Summary. MOS Transistor Theory. Introduction. MOS Device Design Equation. The Complemenatry CMOS Inverter-DC Characteristics. Alternate CMOS Inverters. The Differential Stage. The Transmission Gate. Bipolar Devices. CMOS Processing Technology. Silicon Semiconductor Technology: An Overview. CMOS Technologies. Layout Design Rules. CAD Issues. Circuit Characterization and Performance Estimation. Introduction. Resistance Estimation. Capacitance Estimation. Inductance. Switching Characteristics. CMOS Gate Transistor Sizing. Power Consumption. Determination of Conductor Size. Charge Sharing. Design Margining. Yield. Scaling of MOS Transistor Dimensions. CMOS Circuit and Logic Design. Introduction. CMOS Logic Structures. Basic Physical Design of Simple Logic Gates. Clocking Strategies. Physical and Electrical Design of Logic Gates. 10 Structures. Structured Design Strategies. Introduction. Design Economics. Design Strategies. Design Methods. CMOS Chip Design Options. Design Capture Tools. Design Verification Tools. CMOS Test Methodolgies. Introduction. Fault Models. Design for Testability. Automatic Test Pattern Generation. Design for Manufacturability. CMOS Subsystem Design. Introduction. Adders and Related Functions. Binary Counters. Multipliers and Filter Structures. Random Access and Serial Memory. Datapaths. FIR and IIR Filters. Finite State Machines. Programmable Logic Arrays. Random Control Logic.