This paper describes how model checking has been integrated into an industrial hardware design process. We present an application oriented specification language for assumption/commitment style properties and an abstraction algorithm that generates an intuitive and efficient representation of synchronous circuits. These approaches are embedded in our Circuit Verification Environment CVE. They are demonstrated on two industrial applications.

/pdf/model-checking-in-industrial-hardware-design-nzo3xt2lmz.pdf

Model Checking in Industrial Hardware Design

Timing diagrams are widely used in industrial practice to express precedence and timing relationships amongst a collection of signals. This graphical notation is often more convenient than the use of temporal logic or automata. We introduce a class of timing diagrams called Regular Timing Diagrams (RTD's). RTD's have a precise syntax, and a formal semantics that is simple and corresponds to common usage. Moreover, RTD's have an inherent compositional structure, which is exploited to construct an efficient algorithm for model checking a RTD with respect to a system description. The algorithm has time complexity that is linear in the system size and a small polynomial in the representation of the diagram. The algorithm can be easily used with symbolic (BDDbased) model checkers. We illustrate the workings of our algorithm with the verification of a simple master-slave system.

/pdf/efficient-decompositional-model-checking-for-regular-timing-2nfqjld3wj.pdf

Efficient Decompositional Model Checking for Regular Timing Diagrams

In this article we provide a practical transformational approach to the synthesis of correct synchronous digital hardware designs from high-level specifications. We do this while taking into account the complete life cycle of a design from early prototype to full custom implementation. Besides time-to-market, both flexibility with respect to target architecture and efficiency issues are addressed by the methodology. The utilization of user-selected behavior-preserving transformation steps ensures first-time-right design while exploiting the experience, flexibility, and creativity of the designer.To ensure that design transformations are indeed behavior-preserving a novel mechanized approach to the specification and verification of design transformations on control data flow graphs which is independent of a specific behavioral model or graph size has been developed.As a demonstration of an industrial application we use a video processing algorithm needed for the conversion from a line-interlaced to progressively scanned video format. Both a video signal processor-based prototype implementation as well as a very efficient full custom implementation are developed starting from a single high-level behavioral specification of the algorithm in VHDL. Results are compared with those previously obtained using different tools and methodologies.

From VHDL to efficient and first-time-right designs: a formal approach

Model checking is an automated approach to the formM verification of hardware and software. To allow model checking tools to be used by the hardware or software designers themselves, instead of by verification experts, the tools should support specification methods that correspond closely to the common usage. For hardware systems, timing diagrams form such a commonly used and visually appealing specification method. In this paper, we introduce a class of synchronous timing diagrams with a syntax and a formal semantics that is close to the informal usage. We present an efficient, decompositional algorithm for model checking such timing diagrams. This algorithm has been implemented in a user-friendly tool called RTDT (the Regular Timing Diagram Translator). We have applied this tool to verify several properties of Lucent's PCI synthesizable core.

Model Checking Synchronous Timing Diagrams

VHDL/S—integrating statecharts, timing diagrams, and VHDL

Introducing structure into behavioural descriptions obtained from timing diagram specifications

Timing diagrams with data and timing annotations are introduced as a language for specifying interface circuits In this paper we describe how to generate VHDL from timing diagrams in order to get a hardware implementation or simply to get VHDL code for stimuli to be used in a test bench By giving timing diagrams a formal semantics in terms of T-LOTOS, we can apply optimizing correctness-preserving transformation steps In order to produce good VHDL code on the way to a hardware implementation it is of great importance to introduce structures into the final description that are not automatically derivable from a given specification The designer is rather asked to assist in introducing a structure by applying a bottom-up interactive synthesis procedure

W. D. Tiedemann

Papers

Introducing structure into behavioural descriptions obtained from timing diagram specifications

Transformation of timing diagram specifications into VHDL code