Proceedings ArticleDOI
Transformation of timing diagram specifications into VHDL code
W. Grass,C. Grobe,S. Lenk,W. D. Tiedemann,Carlos Delgado Kloos,Andrés Marín,Tomás Robles +6 more
- pp 659-668
TLDR
This paper describes how to generate VHDL from timing diagrams in order to get a hardware implementation or simply to get V HDL code for stimuli to be used in a test bench by giving timing diagrams a formal semantics in terms of T-LOTOS.Abstract:
Timing diagrams with data and timing annotations are introduced as a language for specifying interface circuits In this paper we describe how to generate VHDL from timing diagrams in order to get a hardware implementation or simply to get VHDL code for stimuli to be used in a test bench By giving timing diagrams a formal semantics in terms of T-LOTOS, we can apply optimizing correctness-preserving transformation steps In order to produce good VHDL code on the way to a hardware implementation it is of great importance to introduce structures into the final description that are not automatically derivable from a given specification The designer is rather asked to assist in introducing a structure by applying a bottom-up interactive synthesis procedureread more
Citations
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Book ChapterDOI
Efficient Decompositional Model Checking for Regular Timing Diagrams
TL;DR: This work introduces a class of timing diagrams called Regular Timing Diagrams (RTD's), which have a precise syntax, and a formal semantics that is simple and corresponds to common usage, which are exploited to construct an efficient algorithm for model checking a RTD with respect to a system description.
Book ChapterDOI
Model Checking Synchronous Timing Diagrams
TL;DR: This paper introduces a class of synchronous timing diagrams with a syntax and a formal semantics that is close to the informal usage, and presents an efficient, decompositional algorithm for model checking such timing diagrams.
Book ChapterDOI
Containing of Regular Languages in Non-Regular Timing Diagram Languages is Decidable
TL;DR: It is established that a class of parametrically constrained timing properties can be verified algorithmically against finite-state systems and containment by a regular language is shown decidable for aclass of language properties expressible in timing diagram logic.
Proceedings ArticleDOI
Hardware synthesis from requirement specifications
K. Feyerabend,Rainer Schlör +1 more
TL;DR: The theory and implementation of a novel system for hardware synthesis from requirement specifications expressed in a graphical specification language called Symbolic Timing Diagrams (STD) is described and the feasibility of the approach and experimental results obtained are shown.
Proceedings ArticleDOI
A prover for VHDL-based hardware design
TL;DR: The aim of this paper is to explain how proofs about generic (parameterized) designs are performed in the prover, using a combination of automatic and interactive reasoning.
References
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