Josephson devices are potential elements for ultra-fast computers. Rather complex logic and memory circuits have been realized. Here quantum interference devices with improved speed and power performance are discussed. Latching and non-latching logic operation is possible and experiments with non-latching circuits are reviewed. Memory applications of quantum interference devices are also considered.

Josephson quantum interference computer devices

A family of novel Josephson logic circuits called current injection logic (CIL) is presented. In contrast to previous approaches, it combines magnetically coupled interferometers with novel nonlinear injection gates to obtain ultra-fast logic speeds, wide margins, and greater fan-in and fan-out capabilities. Fastest logic delay of 30 ps/gate is measured averaged over two- and four-input OR and AND gates (average fan-in=4.5, average fan-out=2.5) fabricated using 2.5 /spl mu/m nominal design rules. The average power dissipation of these experimental circuits is 6 /spl mu/W/gate. An unprecedented logic delay of 13 ps/stage is measured on a chain of two-input OR gates, and the logic delay for a circuit consisting of two two-input OR gates, the outputs of which are `AND'ed, is measured at 26 ps. The experimental results are found to be in excellent agreement with delay estimates based upon computer simulations.

A 30-ps Josephson current injection logic (CIL)

An inverting, nonlatching switching device capable of analog as well as digital signal amplification is investigated experimentally and theoretically (numerical simulations). The device reported is based on the dynamic properties of long Josephson junctions. It is shown that current gain of the order of 5 can be achieved in a 2.5‐μm technology, for small resistive loads of the order of 0.5 Ω.

A Josephson vortex‐flow device

An experimental memory model for investigating the feasibility of a 16K RAM memory with Josephson junctions was fabricated and tested. There are nearly 4500 Josephson junctions in the design which includes array, line drivers, and address decoders. Storage element is a single flux-quantum (SFQ) cell arranged in a 2K array. Drivers and decoders are based on the principle of current steering in superconducting loops, which is a medium speed but low power approach. The measured read-access time of the model is approximately 10 ns. Power dissipation of the unselected chip is zero, whereas for a read/write cycle time of 30 ns, it amounts to about 10 /spl mu/W. Results indicate that a 16K chip is feasible electrically. The estimated access time and power dissipation are 15 ns and 40 /spl nu/W, respectively.

Model for a 15 ns 16K RAM with Josephson junctions

Josephson 1-kbit random access memories (RAM's) have been fabricated using Nb multilayer planarization technology with Nb/AlO/sub x//Nb junctions and Mo resistors. The RAM design has been reported previously. The RAM consists of a 32*32-bit nondestructive readout (NDRO) memory cell array and peripheral circuits. The NDRO memory cell consists of a loop storing three flux quanta and two 3-junction interferometer gates. The peripheral circuits consist of decoders with address inverters, drivers, a sense circuit and reset circuits, where resistor-coupled Josephson logic (RCJL) circuits are used as basic circuits. The RAM circuit size is 4.4*4.4 mm/sup 2/, and the memory cell size is 65*65 mu m/sup 2/. About 10000 Nb/AlO/sub x//Nb junctions with 1030-A/cm/sup 2/ critical current density were contained in the RAM. Minimum line and space widths were 3 and 2 mu m, respectively. The Mo resistors had 1.2 approximately 1.3 Omega sheet resistance. About 40 percent of the bits were successfully operated with a +or-18-percent bias margin. A minimum 570-ps access time with 13-mW power dissipation was obtained for the highest peripheral circuit bias conditions. >

570-ps 13-mW Josephson 1-kbit NDRO RAM

The design and testing of an experimental fully decoded 64-bit Josephson NDRO (nondestructive readout) RAM chip are described. Tree decoders were used to access the memory cells. The basic memory cell was a ring cell containing a single write gate. The chips were built in a coarse 25 /spl mu/m technology since neither speed nor density were stressed in this study. An access time of 4 ns with full margins and of 2.3 ns with reduced margins were demonstrated. The corresponding full memory cycle times were 5 and 3.5 ns, respectively. Good agreement with computer simulations was obtained throughout.

W.H. Henkels

Papers

An experimental 64-bit decoded Josephson NDRO random access memory