In this paper, a new design of low noise, low-power consumption charge amplifier is described Theoretical results show that a total output noise voltage reduction of 0261 mV has been obtained This value corresponds to a 46% reduction compared to the noise performance of a conventional charge amplifier A complete readout system including the proposed charge amplifier has been realized in a 08-/spl mu/m semiconductor on insulator (SOI) bipolar complementary metal-oxide-semiconductor (BiCMOS) process A measured noise performance of 450 electrons at 0 pF with a slope of 44 electrons/pF for a shaping time of 45 ns, a conversion gain of 20 mV/fC and 1-mW power consumption have been obtained

Design and performance of a low-noise, low-power consumption CMOS charge amplifier for capacitive detectors

A low-voltage, low-noise, charge-sensitive preamplifier (CSA) for particle tracking using a silicon strip detector was designed. The preamplifier was optimised in terms of the total output noise performance using a noise minimisation technique based on the MOSFET noise small signal equivalent circuit and readout front-end noise optimisation criteria valid in the strong inversion region. The preamplifier was designed and fabricated in a 0.35 m CMOS process by Austria Mikro Systeme for a specific silicon strip detector of 2 pF capacitance for X-ray spectroscopy. The circuit exhibits satisfactory performance compatible to the specific low-energy radiation detection application. Particularly, the CSA provides an equivalent noise charge of 254 e + 13.5+e - /pF, consumes 165 muW and achieves an output conversion gain equal to 2.81 mV/fC and a linearity <0.57 . Analysis is supported by extensive measurement results confirming the circuit characteristics and their flexibility to be used in a variety of readout applications.

Noise optimised charge-sensitive CMOS amplifier for capacitive radiation detectors

An analog frontend block of a VLSI readout chip, dedicated to high spatial resolution X or beta ray imaging, using capacitive silicon detectors, is described. In the present prototype, an ENC noise of 343 electrons at 0 pF with a noise slope of 28 electrons/pF has been obtained for a peaking time of 10 μs, a 37 mV/fC conversion gain, a 3.5 V power supply and a 150 μW/channel power consumption.

A Very Low Power Consumption, Low Noise Analog Readout Chip for Capacitive Detectors with a Power Supply of 3.3 V

In this paper, the design of a novel low-noise front-end readout circuit for Cadmium zinc telluride (CdZnTe) X-ray and γ-ray detectors is described. The front-end readout circuits include the charge sensitive amplifier (CSA) and the CR-RC shaper is implemented in TSMC 0.35 μm mixed-signal CMOS technology. The die size of the prototype chip is 4.9 mm × 2.2 mm. The simulation results show that, the noise performance is 46 electrons + 10 electrons/pF, and power consumption is 1.65 mW per channel.

https://file.scirp.org/pdf/JSIP_2013050811225418.pdf

Design of a Low-Noise Front-End Readout Circuit for CdZnTe Detectors

A two-stage charge sensitive amplifier structure suitable for silicon radiation detector with large capacitance is proposed. It has the advantage that the integration capacitor can be large to reduce the gain sensibility to detector capacitance variation without any stability problem. The feasibility of the proposed circuit is verified by comparing the simulation results with the conventional one-stage charge sensitive amplifier. A prototype of 16-channel readout circuit for electron collection has been taped out in a 0.35μm CMOS technology with a power supply of 5V. The area is 2.5×1.54mm2 with 42 pads and the power dissipation is 60mW.

http://ieeexplore.ieee.org/iel7/6459619/6466666/06467724.pdf

Radiation detector readout circuit with two-stage charge sensitive amplifier

A high-performance, low-noise charge preamplifier integrated circuit is designed and tested for the Superconducting Super Collider. The amplifier is fabricated in a new dielectrically isolated (DI), radiation-hardened, very-high-frequency (VHF) BIFET IC process technology from Harris Corporation. This new process provides n-p-n, p-n-p, and p-channel JFET devices which are both radiation-hardened, tested to 3 Mrad of total gamma ray exposure and 3*10/sup 14//cm/sup 2/ neutron dosage, and provides high-frequency performance. The new charge preamplifier provides improved performance with an output rise time of 65 ns, input inferred noise of 28.6 mu V, or 3575 electrons, and power dissipation less than 33.7 mW. The circuit design is discussed with attention given to those design characteristics needed to specifically accommodate low noise with the new radiation-hardened process. >

Design of a high-performance, low-noise charge preamplifier

Pulse shaper circuits are often needed to reduce noise levels and condition signals for processing. The noise attributes of several time-invariant and time-variant pulse shapers are compared for a charge preamplifier designed for atomic calorimetry measurements. Pulse shapers reviewed are equally applicable to a wide range of measurement applications. Previous work examining the noise attributes of pulse shapers has been based on simplistic noise modeling. The contribution of this work is a comparison of the noise characteristics of a reasonably complete set of pulse shaper configurations using the noise modeling available through the SPICE circuit simulator. A pulse shaper is selected for fabrication, and experimental results are discussed. >

http://ieeexplore.ieee.org/iel1/19/6447/00252533.pdf

W.P. Wheless

Papers

Design of a high-performance, low-noise charge preamplifier

Pulse shaping for low-noise, charge preamplifiers