Wet anisotropic etching based silicon micromachining is an important technique to fabricate freestanding (e.g. cantilever) and fixed (e.g. cavity) structures on different orientation silicon wafers for various applications in microelectromechanical systems (MEMS). {111} planes are the slowest etch rate plane in all kinds of anisotropic etchants and therefore, a prolonged etching always leads to the appearance of {111} facets at the sidewalls of the fabricated structures. In wet anisotropic etching, undercutting occurs at the extruded corners and the curved edges of the mask patterns on the wafer surface. The rate of undercutting depends upon the type of etchant and the shape of mask edges and corners. Furthermore, the undercutting takes place at the straight edges if they do not contain {111} planes. {100} and {110} silicon wafers are most widely used in MEMS as well as microelectronics fabrication. This paper reviews the fabrication techniques of convex corner on {100} and {110} silicon wafers using anisotropic wet chemical etching. Fabrication methods are classified mainly into two major categories: corner compensation method and two-steps etching technique. In corner compensation method, extra mask pattern is added at the corner. Due to extra geometry, etching is delayed at the convex corner and hence the technique relies on time delayed etching. The shape and size of the compensating design strongly depends on the type of etchant, etching depth and the orientation of wafer surface. In this paper, various kinds of compensating designs published so far are discussed. Two-step etching method is employed for the fabrication of perfect convex corners. Since the perfectly sharp convex corner is formed by the intersection of {111} planes, each step of etching defines one of the facets of convex corners. In this method, two different ways are employed to perform the etching process and therefore can be subdivided into two parts. In one case, lithography step is performed after the first step of etching, while in the second case, all lithography steps are carried out before the etching process, but local oxidation of silicon (LOCOS) process is done after the first step of etching. The pros and cons of all techniques are discussed.

/pdf/a-comprehensive-review-on-convex-and-concave-corners-in-5f1mlgjztz.pdf

A comprehensive review on convex and concave corners in silicon bulk micromachining based on anisotropic wet chemical etching

In this research, we have studied the various shapes of corner compensation structures such as triangles, squares as well as 〈1 1 0〉 and oriented beams for use with pure and surfactant added tetramethyl ammonium hydroxide (TMAH) solutions. The etchant concentrations of 10%, 20% and 25% were used with and without a small amount of surfactant NC-200 (0.1% of the total volume of the etchant). This surfactant contains 100% polyoxyethylene-alkyl-phenyl-ether with a hydrophobic head ‘CH 3 (CH 2 ) 8 –C 6 H 4 ’ and a hydrophilic tail ‘O(CH 2 CH 2 O) 20 H’. As the etching characteristics (such as etch rate, convex corner undercutting and etching anisotropy) of pure TMAH change dramatically when a small amount of surfactant is added, all the designs proposed for pure TMAH (or KOH) cannot be adopted for surfactant added TMAH. Among all the compensating designs, the triangular shaped geometry is found to be the optimal choice for the surfactant added 25% TMAH solution. The optimized design is successfully used for demonstrating the fabrication of grooves for chip isolation and mesa structures surrounded by bent V-grooves where limited space is available for the compensating pattern. Furthermore, the NC-200 added 25% TMAH was also used to fabricate microfluidic channels, microstructures with rounded concave and sharp convex corners, and a 45° mirror with smooth sidewalls.

Study of corner compensating structures and fabrication of various shapes of MEMS structures in pure and surfactant added TMAH

This paper presents micromachined solenoid inductors that are fabricated in a standard CMOS silicon substrate (with a resistivity of 1-8 Omega  cm) The solenoid is concavely embedded in a silicon cavity with the silicon wafer surface remaining a plane, and mechanically suspended to form an air gap from the bottom of the silicon cavity In addition to facilitating flip-chip packaging, this so-called "concave-suspending" technique effectively depresses the substrate effects including eddy current and capacitive coupling between the coil and the substrate, therefore contributing to both high Q -factor and high resonant frequency of the inductors for high-performance radio-frequency (RF)/microwave integrated circuit applications Various inductors with different solenoid layouts, eg, several shapes of curved solenoids, have been successfully fabricated by using a post-CMOS microelectromechanical systems process that employs copper electroplating, tetra-methyl-ammonium hydroxide (TMAH) + iso- propanol etching and compensation control for convex-corner undercutting, photoresist spray coating, XeF2 gaseous etching, and other steps A lumped circuit model that accounts for inter- turn fringing capacitance, capacitance between the coil and the substrate, substrate ohmic loss and substrate capacitance, etc, is derived for the solenoid inductors The accuracy of the model is confirmed by the testing results and can be used for optimal design of the inductors By S-parameter testing, various types of inductors with different solenoid layouts have been evaluated The solenoid inductors generally exhibit improved RF performance in Q-factor and self-resonance frequency compared to their conventional counterparts

High- $Q$ Solenoid Inductors With a CMOS-Compatible Concave-Suspending MEMS Process

This paper describes high Q, free-standing, narrow beam supported film bulk acoustic-wave resonators (FBARs) fabricated with silicon micromachining. The resonators are composed of metal/ZnO/metal/Si/sub x/N/sub y/ (or metal/ZnO/metal) composite layers, which are suspended by narrow Si/sub x/N/sub y//metal (or metal) beams to minimize energy leakage to the substrate. A layer of 0.5-/spl mu/m thick parylene deposited and patterned over the Si/sub x/N/sub y//metal (or metal) beams is proven to enhance the sturdiness of the free-standing structure greatly. The highest Q (quality) factors we have obtained with this new structure are 1,587 and 769 at 2.7 and 5.1 GHz, respectively. This paper also describes the effect of removing the silicon-nitride support layer (to form air-backed FBARs that do not use any supporting layer below or above piezoelectric the ZnO layer sandwiched by two metal layers). The electromechanical coupling constant (K/sup 2//sub t/) is improved from 3.2% to 6.8% when a 0.9-/spl mu/m thick silicon-nitride support layer is removed.

Micromachined acoustic wave resonator isolated from substrate

Presented in this brief is a concave-suspended solenoid inductor that can be post-CMOS integrated into a low-resistivity silicon substrate using a novel radio frequency integrated circuit (RFIC)-compatible micromachining technology. The three-mask processes include photoresist spray coating, XeF2 gaseous etching and copper electroplating, etc. The fabricated 11.5-turn inductor is measured with 2.96-nH inductance at 5.35 GHz, where the peak Q-factor is as high as about 45. Even with a compact layout (50% area occupation saved), the 8.5-turn inductor is still measured with 2.78 nH and peak Q of about 28 at 4.90 GHz. Both finite element simulation and shock testing results show that the suspended inductor is almost free of influence from environmental vibration and shock. Featuring high-Q performance and robust properties, the RFIC-compatible inductors are promising for high-performance RFIC applications

Concave-Suspended High- $Q$ Solenoid Inductors With an RFIC-Compatible Bulk-Micromachining Technology

This paper reports a new category of high-Q edge-suspended inductors (ESI) that are fabricated using CMOS-compatible micromachining techniques. This structure was designed based on the concept that the current was crowded at the edges of the conducting metal wires at high frequencies due to the proximity effect. The substrate coupling and loss can be effectively suppressed by removing the silicon around and underneath the edges of the signal lines. Different from the conventional air-suspended inductors that have the inductors built on membranes or totally suspended in the air, the edge-suspended structures have the silicon underneath the center of the metal lines as the strong mechanical supports. The ESIs are fabricated using a combination of deep dry etching and anisotropic wet etching techniques that are compatible with CMOS process. For a three-turn 4.5-nH inductor, a 70% increase (from 6.8 to 11.7) in maximum Q-factor and a 57% increase (from 9.1 to 14.3 GHz) in self-resonance frequency were obtained with a 11-/spl mu/m suspended edge in 25-/spl mu/m-wide lines.

CMOS-compatible micromachined edge-suspended spiral inductors with high Q-factors and self-resonance frequencies

This paper reports the micromachining techniques for fabricating edge-suspended RF/microwave passive components, which are proposed to deliver enhanced performance without sacrificing their mechanical strength and reliability. The fabrication incorporates ICP-DRIE dry etching and TMAH anisotropic etching techniques, which are both CMOS compatible. The edge-suspended structures were realized by a TMAH solution consisting of 5 wt% TMAH, 1.6 wt% Si and 0.5 wt% (NH4)2S2O8. This solution offers effective etching of silicon along the {100} and {110} planes, while having negligible etching on aluminum and {111} planes. The layout requirement for achieving edge-suspended passive components is also outlined on the basis of the analysis of the anisotropic etching along different crystal orientations. Using the techniques described here, high performance spiral inductors and coplanar waveguides (CPW) with significantly reduced loss are demonstrated. For a three-turn 4.5 nH inductor, a 70% increase (from 6.8 to 11.7) in maximum Q-factor and a 57% increase (from 9.1 GHz to 14.3 GHz) in self-resonance frequency are obtained with an 11 µm suspended edge in 25 µm wide lines compared to the conventional inductors without being micromachined. A 50 Ω edge-suspended CPW exhibits a reduction in insertion loss, from 2.4 dB mm−1 in a conventional CPW to 0.4 dB mm−1 at 39 GHz.

CMOS-compatible micromachining techniques for fabricating high-performance edge-suspended RF/microwave passive components on silicon substrates

This paper reports a new category of high-Q edgesuspended inductors (ESI) that are realized using CMOS-compatible micromachining techniques. This structure was designed based on the concept that the current was crowded at the edges of the conducting metal wires at high frequencies due to the proximity effect. Sinee the coupling to the loti resistivity silieon substrate is dominated by the current carrying parts (the edges), the substrate coupling and loss can be effectively suppressed by removing the silicon around and underneath the edges of the signal lines. DilTerent from the conventional air-suspended inductors that have the inductors built on membrane or totally suspended in the air, the edgesuspended structures have the silicon underneath the center of the metal lines as the strong mechanical supports. The edge-suspension structures are fabricated using a combination of deep dry etching and anisotropic wet etching techniques that are compatible with CMOS process. For a threeturn 45nH inductor, a 70% increase (from 6.8 to 11.7) in maximum Q- factor, a 57% inerease (from 9.1 GHz lo 14.3 GHz) in self- resonance frequency are obtained with a 11 pm suspended edge in 25 pm wide lines.

High-Q CMOS-Compatible Micromachined Spiral Inductors Edge- Suspended

This paper reports a new category of high-Q edge-suspended inductors (ESI) that are realized using CMOS-compatible micromachining techniques. This structure was designed based on the concept that the current was crowded at the edges of the conducting metal wires at high frequencies due to the proximity effect. Since the coupling to the low resistivity silicon substrate is dominated by the current carrying parts (the edges), the substrate coupling and loss can be effectively suppressed by removing the silicon around and underneath the edges of the signal lines. Different from the conventional air-suspended inductors that have the inductors built on membrane or totally suspended in the air, the edge-suspended structures have the silicon underneath the center of the metal lines as the strong mechanical supports. The edge-suspension structures are fabricated using a combination of deep dry etching and anisotropic wet etching techniques that are compatible with CMOS process. For a three-turn 4.5-nH inductor, a 70% increase (from 6.8 to 11.7) in maximum Q-factor, a 57% increase (from 9.1 GHz to 14.3 GHz) in self-resonance frequency are obtained with a 11 /spl mu/m suspended edge in 25 /spl mu/m wide lines.

High-Q CMOS-compatible micromachined edge-suspended spiral inductors

This paper reports high performance edge-suspended passive components realized by CMOS-compatible micromachining. The operation principle is described in detail. Edge-suspended inductors (ESIs) and CPWs (ESCPWs) are fabricated using a combination of deep dry etching and anisotropic wet etching techniques. For a three-turn 4.5-nH inductor, a 70% increase (from 6.8 to 11.7) in maximum Q-factor and a 57% increase (from 9.1 GHz to 14.3 GHz) in self-resonance frequency are obtained with a 11 /spl mu/m suspended edge in 25 /spl mu/m wide lines. A 50 /spl Omega/ CPW exhibits a reduction in insertion loss, from 2.4dB/mm to 0.4dB/mm at 39 GHz.

Wai Cheong Hon

Papers

CMOS-compatible micromachined edge-suspended spiral inductors with high Q-factors and self-resonance frequencies

CMOS-compatible micromachining techniques for fabricating high-performance edge-suspended RF/microwave passive components on silicon substrates

High-Q CMOS-Compatible Micromachined Spiral Inductors Edge- Suspended

High-Q CMOS-compatible micromachined edge-suspended spiral inductors

High-performance edge-suspended spiral inductors and CPWs on CMOS-grade silicon substrates