The communication system includes a hybrid fiber/coax distribution network. A head end provides for downstream transmission of telephony and control data in a first frequency bandwidth over the hybrid fiber/coax distribution network and reception of upstream telephony and control data in a second frequency bandwidth over the hybrid fiber/coax distribution network. The head end includes a head end multicarrier modem for modulating downstream telephony information on a plurality of orthogonal carriers in the first frequency bandwidth and demodulating upstream telephony information modulated on a plurality of orthogonal carriers in the second frequency bandwidth. The system includes service units, operatively connected to the hybrid fiber/coax distribution network for upstream transmission of telephony and control data and for receipt of the downstream control data and telephony. Also provided is a method and apparatus for performing a Fast Fourier Transform (FFT).

Communication system with multicarrier telephony transport

A high-speed VLSI multiplication algorithm internally using redundant binary representation is proposed. In n bit binary integer multiplication, n partial products are first generated and then added up pairwise by means of a binary tree of redundant binary adders. Since parallel addition of two n-digit redundant binary numbers can be performed in a constant time independent of n without carry propagation, n bit multiplication can be performed in a time proportional to log2 n. The computation time is almost the same as that by a multiplier with a Wallace tree, in which three partial products will be converted into two, in contrast to our two-to-one conversion, and is much shorter than that by an array multiplier for longer operands. The number of computation elements of an n bit multiplier based on the algorithm is proportional to n2. It is almost the same as those of conventional ones. Furthermore, since the multiplier has a regular cellular array structure similar to an array multiplier, it is suitable for VLSI implementation. Thus, the multiplier is excellent in both computation speed and regularity in layout. It can be implemented on a VLSI chip with an area proportional to n2 log2 n. The algorithm can be directly applied to both unsigned and 2's complement binary integer multiplication.

High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree

An object is to provide a method for manufacturing a semiconductor device, in which the number of photolithography steps can be reduced, the manufacturing process can be simplified, and manufacturing can be performed with high yield at low cost A method for manufacturing a semiconductor device includes the following steps: forming a semiconductor film; irradiating a laser beam by passing the laser beam through a photomask including a shield for shielding the laser beam; subliming a region which has been irradiated with the laser beam through a region in which the shield is not formed in the photomask in the semiconductor film; forming an island-shaped semiconductor film in such a way that a region which is not irradiated with the laser beam is not sublimed because it is a region in which the shield is formed in the photomask; forming a first electrode which is one of a source electrode and a drain electrode and a second electrode which is the other one of the source electrode and the drain electrode; forming a gate insulating film; and forming a gate electrode over the gate insulating film

Method for Manufacturing Semiconductor Device

A programmable logic integrated circuit device (“PLD”) includes programmable logic and a dedicated (i.e., at least partly hard-wired) digital signal processing region for performing or at least helping to perform digital signal processing tasks that are unduly inefficient to implement in the more general-purpose programmable logic and/or that, if implemented in the programmable logic, would operate unacceptably or at least undesirably slowly. The digital signal processing region may include multiple digital signal processing stages. The digital signal processing region may include a multiplier stage and one ore more stages that can operate in combination with the multiplier stage. The digital signal processing region has a plurality of modes such as for providing multiply-and-accumulate operation, multiply-and-add operation, etc.

Devices and methods with programmable logic and digital signal processing regions

A transistor structure comprising an active semiconductor layer with metal source and drain contacts (20, 22) formed in electrical contact with the active layer. A gate contact (26) is formed between the source and drain contacts for modulating electric fields within the active layer. A spacer layer (24) is formed above the active layer and a conductive field plate (28) formed above the spacer layer, extending, a distance Lf from the edge of the gate contact toward the drain contact. The field plate is electrically connected to the gate contact.

Wide bandgap transistor devices with field plates

A monolithic high performance processor for computing digital signal processing algorithms based on the Fast Fourier Transform. The monolithic processor employs an array of bit-serial multipliers which cooperate with bit-serial adder/substractors to produce fast results with great precision, with reduced printed-circuit board space, and with low power requirements. The processor uses local asynchronous control and simple interfacing with the host computer. The processor, which is applicable to a broad spectrum of digital signal processing, including digital audio, radar/sonar, seismic and speech processing, operates in a variety of modes which allow the device to perform Fast Fourier Transforms, Inverse Fast Fourier Transforms, windowing, multiplication, Finite Impulse Response filtering, convolution and correlation.

High performance signal processor

A method of fabricating MESFET devices having a submicron line gate electrode is disclosed. The method includes the formation of a single layer of resist material on a semiconductor surface; formation of a resist cavity through optical lithography, the cavity exposing a selected portion of the semiconductor surface; depositing by way of angled evaporation at least one gate wall within said resist cavity, the gate wall defining a shaped gate cavity; depositing gate electrode material within the gate cavity, and removing the resist material. In one embodiment of the invention the gate wall is removed from the gate electrode material, leaving a free-standing electrode. In another embodiment, the gate wall is a permanent part of the electrode structure.

Fabrication of metal lines for semiconductor devices

A heterojunction transistor doped to form a specially-shaped emitter-base conduction band step or spike is disclosed. The potential barrier is then utilized to accelerate electrons across the base region at the maximum velocity obtainable without scattering electrons to the upper valleys. In this manner the electrons bay be transported across the base region virtually without collisions and at a velocity approximately 10 times that of normal electron diffusion across the base region, thus increasing the frequence response of the transistor.

Ballistic heterojunction bipolar transistor

The paper presents techniques to increase the speed of fixed-point parallel multipliers and reduce the multiplier chip size for VLSI realizations. It is shown that a higher order (octal) version of the Booth’s Algorithm will lead to significant improvements in speed, coupled with a decrease of chip area and power consumption, as compared to the modified (quaternary) version of the Booth’s Algorithm presently used in or proposed for monolithic multipliers. In addition, further speed improvements can be obtained by using Wallace trees or optimal Dadda types of realizations.

Fixed-Point High-Speed Parallel Multipliers in VLSI

This paper describes the Cornell University Signal Processor (CUSP), a 60 000 transistor 2-/spl mu/m CMOS processor custom designed to compute the Fast Fourier Transform (FFT) and related algorithms. Operating on a 50-MHz clock, the bit-serial arithmetic hardware on a CUSP chip performs over 15 million 20 X 20 bit multiplications per second and computes a 1024 point FFT in 1.33 ms. The chip architecture is presented along with a description of the arithmetic, control, and fault detection circuitry. The inclusion of these components on a single chip is shown to allow large fault tolerant arrays of CUSP processors to be efficiently employed for high-performance applications.

Walter H. Ku

Papers

High performance signal processor

Fabrication of metal lines for semiconductor devices

Ballistic heterojunction bipolar transistor

Fixed-Point High-Speed Parallel Multipliers in VLSI

CUSP: A 2-/spl mu/m CMOS Digital Signal Processor