Showing papers by "Wayne Luk published in 1996"

A framework for developing parametrised FPGA libraries

Abstract: We suggest that the productivity of FPGA users can be improved by adopting design libraries which are optimally implemented, rich in variety, easy to use, compatible with incremental development techniques and carefully validated. These requirements motivate our research into a framework for developing FPGA libraries involving the industrial-standard VHDL language and the declarative language Ruby. This paper describes the main elements in our framework, and illustrates its application to the Xilinx 6200 series FPGAs.

A Framework for Developing Parameterised FPGA Libraries

Abstract: We suggest that the productivity of FPGA users can be improved by adopting design libraries which are optimally implemented, rich in variety, easy to use, compatible with incremental development techniques and carefully validated. These requirements motivate our research into a framework for developing FPGA libraries involving the industrial-standard VHDL language and the declarative language Ruby. This paper describes the main elements in our framework, and illustrates its application to the Xilinx 6200 series FPGAs.

Deriving two-phase modules for a multi-target hardware compiler

Abstract: This paper adopts the CSP framework for deriving a compilation scheme from a simple imperative language to two-phase modules. Two-phase modules are processes that communicate with one another using two-phase handshake protocols. The two-phase modules generated by our compilation scheme can be implemented as asynchronous or clocked circuits. The derivation techniques have been applied to a concurrent language which is a superset of the language discussed.

Hardware-software cosynthesis for the Riley system

Abstract: Electronic systems containing application specific hardware working alongside an embedded microprocessor are now common place. However, to design such systems quickly and reliably, while exploring the design space sufficiently to ensure near optimal solutions presents many new challenges. The problem is further complicated by reconfigurable hardware such as FPGAs some of which can be dynamically reconfigured. This paper describes some of the tools that we have been developing to assist the design and analysis of such systems. We hope that the collection of tools would form a framework that facilitates rapid design exploration, evaluation and validation. In developing such a framework, it is often helpful to use a specific hardware platform in order to provide a focus for tool development. We have been fortunate to have access to such a hardware platform developed at Hewlett Packard Laboratories Bristol known as the Riley System. While some of the tools developed are specific to Riley, the approach used should be general enough to be applicable to other platforms. (5 pages)

Producing design diagrams from declarative descriptions

Abstract: The declarative language Ruby provides a coherent framework for representing and developing designs. Sketching diagrams for Ruby programs by hand is, however, time- consuming and error-prone. This paper describes a design sketcher which automates the production of a diagram from a Ruby description.© (1996) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

EXTRA: towards the exploitation of eXascale technology for reconfigurable architectures

Abstract: To handle the stringent performance requirements of future exascale-class applications, High Performance Computing (HPC) systems need ultra-efficient heterogeneous compute nodes To reduce power and increase performance, such compute nodes will require hardware accelerators with a high degree of specialization Ideally, dynamic reconfiguration will be an intrinsic feature, so that specific HPC application features can be optimally accelerated, even if they regularly change over time In the EXTRA project, we create a new and flexible exploration platform for developing reconfigurable architectures, design tools and HPC applications with run-time reconfiguration built-in as a core fundamental feature instead of an add-on %The idea is to enable the efficient co-design and joint optimization of architecture, tools, applications, and reconfiguration technology in order to prepare for the necessary HPC hardware nodes of the future EXTRA covers the entire stack from architecture up to the application, focusing on the fundamental building blocks for run-time reconfigurable exascale HPC systems: new chip architectures with very low reconfiguration overhead, new tools that truly take reconfiguration as a central design concept, and applications that are tuned to maximally benefit from the proposed run-time reconfiguration techniques Ultimately, this open platform will improve Europe's competitive advantage and leadership in the field

Serialising heterogeneous and non-factorisable processor arrays

Abstract: This paper presents two classes of transformations for serialising an array of processors. The first serialises a heterogeneous array of size mk to one of size m. The second serialises an array from n to m components where m does not need to be a factor of n. Our transformations are expressed in the Ruby language, which provides a concise notation for capturing the serialised array and the boundary conditions; in particular many design constraints can be represented in the form of conjugate (Q-1; R; Q) or transposed conjugate ([Q,P]-1; R; [P;Q]) expressions. Design trade-offs in performance and resource requirements of various serialisation schemes are discussed.We illustrate our approach using several arithmetic and recursive filter designs, and their implementation using programmable hardware is outlined.