Single-bit continuous-time delta-sigma modulators (CTDSM) using FIR feedback DACs inherit the appealing aspects of both single-bit and multibit designs, without the disadvantage of either approaches. In this work, we give a method for stabilizing a CTDSM that uses an FIR feedback DAC. Further, we show that increasing the number of taps beyond a certain number (dependent on the architecture and oversampling ratio of the modulator) does not improve performance. The results of our analysis are incorporated in the design of a third-order audio CTDSM which achieves a peak A-weighted SNR of 102.3 dB (raw SNR of 98.9 dB) and a spurious-free dynamic range of 106 dB in a 24 kHz bandwidth, while consuming only 280 μW from a 1.8 V supply.

Low Power Design Techniques for Single-Bit Audio Continuous-Time Delta Sigma ADCs Using FIR Feedback

A 12-bit 10 MS/s SAR ADC with enhanced linearity and energy efficiency is presented in this paper. A novel switching scheme (COSS) is proposed to reduce the power consumption and the matching requirement for capacitors in SAR ADCs. The switching energy (including switching energy and reset energy), total capacitance and static performance (INL & DNL) of the proposed scheme are reduced by 98.08%, 75%, and 75%, respectively, compared with the conventional architecture. Based on analysis of the non-linear errors caused by comparator input parasitic capacitance, an improved comparator with push-pull pre-amplifier and output offset storage (OOS) strategy is proposed to diminish non-linearity in the input parasitic capacitance. The offset cancellation signal for the comparator can be generated by asynchronous timing automatically, without any extra clock. Additionally, an SFDR enhancement bootstrap switch is proposed to eliminate the distortion induced by parasitic capacitance and threshold voltage that results in insufficient precision for medium-speed 12-bit ADCs. The proposed ADC was fabricated in a 0.18 $\mu\text{m}$ 1P6M CMOS process, and the measured results show that the ADC achieves an SNDR of 66.9 dB and an SFDR of 75.8 dB with a 10 MS/s sampling rate and consumes 0.82 mW, resulting in a figure of merit (FOM) of 44.2 fJ/conversion-step. The peak DNL error is +0.36/−0.33 LSB, and the peak INL error is +0.55 LSB/−0.6 LSB. The ADC core occupies an active area of only $630\ \mu\text{m}\! \times\! 570\ \mu\text{m}^{2}$ .

A 12-Bit 10 MS/s SAR ADC With High Linearity and Energy-Efficient Switching

This paper presents the first dynamic zoom ADC. Intended for audio applications, it achieves 109-dB DR, 106-dB signal-to-noise ratio, and 103-dB SNDR in a 20-kHz bandwidth, while dissipating only 1.12 mW. This translates into the state-of-the-art energy efficiency as expressed by a Schreier FoM of 181.5 dB. It also achieves the state-of-the-art area efficiency, occupying only 0.16 mm2 in the 0.16- $\mu \text{m}$ CMOS. These advances are enabled by the use of concurrent fine and coarse conversions, dynamic error-correction techniques, and a dynamically biased inverter-based operational transconductance amplifier.

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A Dynamic Zoom ADC With 109-dB DR for Audio Applications

This paper presents a 28 nm CMOS 10 b SHA-less pipelined/SAR hybrid ADC, designed to enable a direct-sampling receiver system. To achieve low power at 5 GS/s, the ADC combines pipelined and SAR quantizers, powered at 1.8 V and 1 V, respectively. A 2.5 b 2-way time-interleaved 2.5 GS/s multiplying digital-to-analog converter (MDAC) is followed by an 8 b 8-way time-interleaved 625 MHz successive-approximation register (SAR). This architecture combines the benefits of both ADC topologies and allows significant power and complexity reduction. The high-speed 2.5 b MDAC front-end simplifies the complexity of time-interleaving (TI) and provides gain for attenuating the 8 b SAR non-idealities, when referred to the ADC input, relaxing its specifications and design. To further reduce power, the 2.5 b MDAC front-end is SHA-less, and an over-range calibration loop that allows operation at multi-GHz input is introduced. A calibration technique is also proposed to align the MDAC and SAR references, whose misalignment would otherwise produce integral non-linearity (INL) degradation. The ADC achieves ${-}$ 61.8 dB THD, 57.1 dB SNR for a 500 MHz input, while for a 2.35 GHz input it achieves ${-}$ 54.7 dB THD, 46.8 dB SNR (55.8 dB SNR excluding the integrated PLL contribution). The time-interleaving spur is ${ 70 dBc. The ADC consumes 150 mW and occupies less than 0.5 mm $^{2}$ .

A 5 GS/s 150 mW 10 b SHA-Less Pipelined/SAR Hybrid ADC for Direct-Sampling Systems in 28 nm CMOS

This paper presents a 5-GS/s 12-way 10-b time-interleaved successive approximation register (SAR) ADC for direct sampling receivers. Proper signal and clock distribution along the multiple channels are utilized to mitigate interchannel bandwidth and timing mismatches. A digitally assisted calibration is introduced to remove the interchannel offset, gain, and timing mismatch. The T-type bootstrapped sampling switches minimize the interchannel crosstalk among top-plate sampling SAR channels and the signal-dependent leakage current during SAR conversion cycles. The power efficiency of this ADC is significantly improved by many design techniques. The merged capacitor switching algorithm leads to high switching efficiency and a smaller area. The modified reference voltage scheme optimizes input common-mode voltage of the comparators. The optimal subradix-2 capacitive DAC results in low-power reference buffers and higher conversion speed. This ADC achieves 49-dB SNR, 52-dB THD, and 42-dB SNDR up to Nyquist frequency at 5 GS/s, consumes 76 mW from 1 V supply, and occupies 0.57 mm $^{{ {2}}}$ in 28 nm CMOS technology. The implemented architecture also demonstrates high scalability to advanced CMOS technology nodes and has even higher power efficiency potential.

A 5-GS/s 10-b 76-mW Time-Interleaved SAR ADC in 28 nm CMOS

A low-power audio delta-sigma modulator (DSM) is presented. Two new techniques are proposed to reduce the overall power dissipation of the modulator: a power-efficient direct-charge-transfer adder is employed, and noise-shaping enhancement is implemented by feeding the differentiated quantization noise to the input of the second integrator. The measured power dissipation is 1.1 mW, the dynamic range is 101.3 dB, the spur-free dynamic range is 112 dB and the signal-to-noise-plus-distortion ratio is 99.3 dB. The power efficiency of this design is among the best in DSMs with high (over 15) ENOBs.

A 101 dB DR 1.1 mW audio delta-sigma modulator with direct-charge-transfer adder and noise shaping enhancement

An on-chip teraohm resistance realization scheme using a switched-capacitor ladder is presented in this paper. Linear tuning of the resistance is realized by controlling the sampling frequency. Using this scheme, a band-pass filter with very low corner frequency (~ 0.3 Hz) was implemented in a fully differential amplifier for a small chip area in a standard CMOS process.

A fully-differential input amplifier with band-pass filter for biosensors

This paper presents a digitally calibrated 12bit 12.5-MS/s successive-approximation-register (SAR) analog-to-digital converter (ADC) intended for low-power wireless communication and medical instrumentation. The performance of the proposed prototype is enhanced by two techniques. A power saving strategy is proposed. Also, several foreground calibration methods for SAR ADCs are proposed to reduce the power dissipation and enhance the conversion accuracy. The design was fabricated in the GlobalFoundries 40 nm CMOS technology. Measurement results showed that after calibration a SFDR of 87.5 dB and a THD improvement of 24.3 dB were achieved.

A 0.45mW 12b 12.5MS/s SAR ADC with digital calibration

New foreground digital calibration methods are proposed for successive approximation register (SAR) analog-to-digital converters (ADCs) to reduce the performance loss due to digital-to-analog converter (DAC) mismatch. A set of calibration coefficients which represent the actual weights of the specified patterns is obtained during foreground calibration, and then used during normal operation to correct the SAR ADC output using only a few multiplexers and an accumulator. The simulation results of a 10-bit SAR ADC with the proposed calibration methods show almost 10 effective number of bits (ENOB) with up to 0.5 % binary-weighted DAC mismatch, and more than 12 dB SNDR improvement for even larger DAC mismatch, compared to that without calibration.

Wei Li

Papers

A 101 dB DR 1.1 mW audio delta-sigma modulator with direct-charge-transfer adder and noise shaping enhancement

A fully-differential input amplifier with band-pass filter for biosensors

A 0.45mW 12b 12.5MS/s SAR ADC with digital calibration

Digital foreground calibration methods for SAR ADCs