Fast states at SiO2/SiC interfaces annealed in NO at 1150–1350 °C have been investigated. The response frequency of the interface states was measured by the conductance method with a maximum frequency of 100 MHz. The interface state density was evaluated based on the difference between quasi-static and theoretical capacitances (C−ψS method). Very fast states, which are not observed in as-oxidized samples, were generated by NO annealing, while states existing at an as-oxidized interface decreased by approximately 90%. The response frequency of the very fast states was higher than 1 MHz and increased when the energy level approaches the conduction band edge. For example, the response frequency (time) was 100 MHz (5 ns) at EC−ET = 0.4 eV and room temperature. The SiO2/SiC interface annealed in NO at 1250 °C showed the lowest interface state density, and NO annealing at a temperature higher than 1250 °C is not effective because of the increase in the very fast states.

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Generation of very fast states by nitridation of the SiO[2]/SiC interface

Recent advances on dielectrics technology for SiC and GaN power devices

https://iopscience.iop.org/article/10.35848/1882-0786/abc787/pdf

Defect engineering in SiC technology for high-voltage power devices

We evaluate and compare the performance and potential of GaAs and of wide and extreme bandgap semiconductors (SiC, GaN, Ga2O3, and diamond), relative to silicon, for power electronics applications. We examine their device structures and associated materials/process technologies and selectively review the recent experimental demonstrations of high voltage power devices and IC structures of these semiconductors. We discuss the technical obstacles that still need to be addressed and overcome before large-scale commercialization commences.

Smart Power Devices and ICs Using GaAs and Wide and Extreme Bandgap Semiconductors

Free electron concentration and carrier mobility measurements on 4H–SiC metal-oxide-semiconductor inversion layers are reported in this article. The key finding is that in state-of-the-art nitrided gate oxides, loss of carriers by trapping no longer plays a significant role in the current degradation under heavy inversion conditions. Rather, it is the low carrier mobility (maximum∼60 cm2 V−1 s−1) that limits the channel current. The measured free carrier concentration is modeled using the charge-sheet model and the mobility is modeled by existing mobility models. Possible mobility mechanisms have been discussed based on the modeling results.

Inversion layer carrier concentration and mobility in 4H–SiC metal-oxide-semiconductor field-effect transistors

The effect of different gate oxide processes on the performance of 4H-SiC MOSFETs has been studied. These processes include different gate oxide depositions (high-temperature oxide, low-temperature oxide, and plasma-enhanced chemical vapor deposition oxide) and annealing processes (oxygen, NO, and ). Various MOS device parameters, particularly, threshold voltage, subthreshold slope, field-effect electron mobility, sheet electron carrier concentration, and Hall mobility, are correlated with various process steps.

Wei Wang

Papers

The Effect of Gate Oxide Processes on the Performance of 4H-SiC MOSFETs and Gate-Controlled Diodes