This invention discloses a customizable logic array including an array of programmable cells having a multiplicity of inputs and a multiplicity of outputs; and customized interconnections providing permanent direct interconnections among at least a plurality of the multiplicity of inputs and at least a plurality of the multiplicity of outputs.

Customizable and programmable cell array

A system includes a semiconductor device. The semiconductor device includes a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layer. The second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands. Each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern.

System comprising a semiconductor device and structure

A device comprising semiconductor memories, the device comprising: a first layer and a second layer of layer-transferred mono-crystallized silicon, wherein the first layer comprises a first plurality of horizontally-oriented transistors; wherein the second layer comprises a second plurality of horizontally-oriented transistors; and wherein the second plurality of horizontally-oriented transistors overlays the first plurality of horizontally-oriented transistors.

Semiconductor device and structure

A method to process an Integrated Circuit device including processing a first layer of first transistors, then processing a first metal layer overlaying the first transistors and providing at least one connection to the first transistors, then processing a second metal layer overlaying the first metal layer, then processing a second layer of second transistors overlaying the second metal layer, wherein the second metal layer is connected to provide power to at least one of the second transistors.

Method for fabrication of a semiconductor device and structure

A programmable memory cell comprised of a transistor located at the crosspoint of a column bitline and a row wordline is disclosed. The transistor has its gate formed from the column bitline and its source connected to the row wordline. The memory cell is programmed by applying a voltage potential between the column bitline and the row wordline to produce a programmed p+ region to form a p-n diode in the substrate underlying the gate of the transistor. Further, the wordline is formed from a buried diffusion N+ layer while the column bitline is formed from a counterdoped polysilicon layer.

High density semiconductor memory cell and memory array using a single transistor and having counter-doped poly and buried diffusion wordline

An apparatus includes an FPGA, which includes a first FPGA tile including a plurality of FGs, a first, second, and third set of routing conductors, and a plurality of IGs. The FGs are arranged in rows and columns with each FG being configured to receive tertiary and regular input signals, perform a logic operation, and generate regular output signals. The third set of routing conductors is coupled to the first set of output ports of the FGs and configured to receive signals, route signals within the FPGA tile, and provide input signals to the third set of input ports of the FGs. The IGs surround the FGs such that one IG is positioned at each end of each row and column. Each IG is coupled to the third set of routing conductors and configured to transfer signals from the third set of routing conductors to outside the first FPGA tile.

Tileable field-programmable gate array architecture

A freeway routing system for connecting input and output ports of interface groups of tiles in a field programmable gate array. The freeway system has a first set of routing conductors configured to transfer signals between the input ports of interface groups in a first tile of the field programmable gate array and the output ports of interface groups of other tiles in the field programmable gate array. The first set conductors include vertical conductors that form intersections with horizontal conductors and programmable interconnect elements located at the intersections of the vertical conductors and horizontal conductors in a diagonal orientation to connect each of the horizontal conductors to one of the vertical conductors.

Weidong Xiong

Papers

Tileable field-programmable gate array architecture

Freeway routing system for a gate array