Patent
Freeway routing system for a gate array
TLDR
A freeway routing system for connecting input and output ports of interface groups of tiles in a field programmable gate array is described in this article. But the freeway system has a first set of routing conductors configured to transfer signals between the input ports of interfaces in a first tile of the field PGA array and the output ports in interfaces in other tiles in the field PPGA array.Abstract:
A freeway routing system for connecting input and output ports of interface groups of tiles in a field programmable gate array. The freeway system has a first set of routing conductors configured to transfer signals between the input ports of interface groups in a first tile of the field programmable gate array and the output ports of interface groups of other tiles in the field programmable gate array. The first set conductors include vertical conductors that form intersections with horizontal conductors and programmable interconnect elements located at the intersections of the vertical conductors and horizontal conductors in a diagonal orientation to connect each of the horizontal conductors to one of the vertical conductors.read more
Citations
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References
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Patent
Programmable logic array integrated circuits
Richard G. Cliff,L. Todd Cope,Cameron McClintock,William Leong,James A. Watson,Joseph Huang,Bahram Ahanin +6 more
TL;DR: In this article, a programmable logic array integrated circuit (PLLIA) is defined, where the logic array blocks are arranged on the circuit in a two-dimensional array, and a conductor network is provided for interconnecting any logic module with any other logic module, and adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network.
Patent
FPGA architecture with repeatable tiles including routing matrices and logic matrices
TL;DR: In this article, a logic element and a portion of the routing matrix are formed as part of a tile, and tiles are joined to form arrays of selectable size, which is achieved by the formation of individual tiles, all of which are identical.
Patent
Programmable logic array integrated circuit devices
TL;DR: In this paper, a programmable logic array integrated circuit (PLCI) device includes a plurality of regions of logic disposed on the device in a two-dimensional array of intersecting rows and columns.
Patent
Hierarchically connectable configurable cellular array
TL;DR: In this paper, a hierarchical routing structure for field programmable gate arrays (FPGA) is presented. And select units for addressing memory bits can be addressed both individually and in large and arbitrary groups.
Patent
Programmable gate array with improved interconnect structure, input/output structure and configurable logic block
TL;DR: In this paper, a programmable gate array with an improved interconnect structure facilitates multi-source networks, communication of signals long distances across the array, and creation of networks in a symmetrical interconnect.