An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

A Three Dimensional Structure (3DS) Memory (100) allows for physical separation of the memory circuits (103) and the control logic circuit (101) onto different layers (103) such that each layer may be separately optimized. One control logic circuit (101) suffices for several memory circuits (103), reducing cost. Fabrication of 3DS memory (100) involves thinning of the memory circuit (103) to less than 50 microns in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections (105) are used. The 3DS memory (100) manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.

Three dimensional structure memory

Ultrathin films of single-walled carbon nanotubes (SWNTs) represent an attractive, emerging class of material, with properties that can approach the exceptional electrical, mechanical, and optical characteristics of individual SWNTs, in a format that, unlike isolated tubes, is readily suitable for scalable integration into devices. These features suggest the potential for realistic applications as conducting or semiconducting layers in diverse types of electronic, optoelectronic and sensor systems. This article reviews recent advances in assembly techniques for forming such films, modeling and experimental work that reveals their collective properties, and engineering aspects of implementation in sensors and in electronic devices and circuits with various levels of complexity. A concluding discussion provides some perspectives on possibilities for future work in fundamental and applied aspects.

http://www.ifc.dicp.ac.cn/library/cailiao/pdf1/11.pdf

Ultrathin Films of Single-Walled Carbon Nanotubes for Electronics and Sensors: A Review of Fundamental and Applied Aspects

Performance of deep-submicrometer very large scale integrated (VLSI) circuits is being increasingly dominated by the interconnects due to decreasing wire pitch and increasing die size. Additionally, heterogeneous integration of different technologies in one single chip is becoming increasingly desirable, for which planar (two-dimensional) ICs may not be suitable. This paper analyzes the limitations of the existing interconnect technologies and design methodologies and presents a novel three-dimensional (3-D) chip design strategy that exploits the vertical dimension to alleviate the interconnect related problems and to facilitate heterogeneous integration of technologies to realize a system-on-a-chip (SoC) design. A comprehensive analytical treatment of these 3-D ICs has been presented and it has been shown that by simply dividing a planar chip into separate blocks, each occurring a separate physical level interconnected by short and vertical interlayer interconnects (VILICs), significant improvement in performance and reduction in wire-limited chip area can be achieved, without the aid of any other circuit or design innovations. A scheme to optimize the interconnect distribution among different interconnect tiers is presented and the effect of transferring the repeaters to upper Si layers has been quantified in this analysis for a two-layer 3-D chip. Furthermore, one of the major concerns in 3-D ICs arising due to power dissipation problems has been analyzed and an analytical model has been presented to estimate the temperatures of the different active layers. It is demonstrated that advancement in heat sinking technology will be necessary in order to extract maximum performance from these chips. Implications of 3-D device architecture on several design issues have also been discussed with special attention to SoC design strategies. Finally some of the promising technologies for manufacturing 3-D ICs have been outlined.

/pdf/3-d-ics-a-novel-chip-design-for-improving-deep-submicrometer-6k9by1rs19.pdf

3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration

This review describes recent groundbreaking results in Si, Si/SiGe, and dopant-based quantum dots, and it highlights the remarkable advances in Si-based quantum physics that have occurred in the past few years. This progress has been possible thanks to materials development of Si quantum devices, and the physical understanding of quantum effects in silicon. Recent critical steps include the isolation of single electrons, the observation of spin blockade, and single-shot readout of individual electron spins in both dopants and gated quantum dots in Si. Each of these results has come with physics that was not anticipated from previous work in other material systems. These advances underline the significant progress toward the realization of spin quantum bits in a material with a long spin coherence time, crucial for quantum computation and spintronics.

/pdf/silicon-quantum-electronics-4bxpe9czeo.pdf

Silicon quantum electronics

Masque de gravure pour l'attaque sèche d'une structure d'électrode

According to the invention, conductive structures are embedded in a substrate and a first layer is formed on a part of sidewalls of each of said conductive structures, a top subarea of the conductive structures not being covered with the first layer. Material of the substrate is removed at least between adjacent conductive structures such that air gaps are formed between adjacent conductive structures, and an insulating second layer is formed on the free subarea of the conductive structures in such a way that the insulating second layer bridges adjacent conductive structures.

Method for the creation of a layer system and layer system

Es wird ein Verfahren zur Verbesserung der Haftung zwischen einer Edelmetallschicht (28) und einer Isolationsschicht (34) vorgeschlagen, bei dem eine Siliziumschicht zwischen der Edelmetallschicht (28) und der Isolationsschicht (34) angeordnet wird. Durch eine thermische Behandlung in oxidativer Umgebung wird die Siliziumschicht siliziert und oxidiert, wobei eine oxidierte Silizidschicht (30') mit starker Durchmischung von Edelmetall und gebildetem Oxid entsteht. Aufgrund der dadurch erreichten relativ grosen inneren Oberflache wird die Haftung zwischen der Edelmetallschicht (28) und der Isolationsschicht (34) verbessert.

A method for manufacturing a device and device having a metal layer and an insulation layer

The invention relates to a hollow structure (100) in an integrated circuit, comprising a first layer (101), a first layer surface (103) and webs (104) disposed thereon one beside the other, said webs including interstices (401), and a second layer (105) and a third layer (106) disposed thereon. The hollow structure further comprises a fourth layer (107) that closes some of the interstices (401), said fourth layer being disposed on the third layer (106) and having a second layer surface (108), the interstices (401) not being closed by the fourth layer (107) being filled with an electrically conducting material.

Hohlraumstruktur und Verfahren zum Herstellen einer Hohlraumstruktur Cavity structure and method of making a hollow structure

A method of manufacturing a strip conductor arrangement (100) • in which a first layer (105) over a substrate (102) with a buried conductor (104) is generated having a first hole (106) and a second hole (107), by means of the two holes (106, 107 ), the substrate (102) is exposed, and wherein at least the first hole (106) is laterally disposed above the at least one buried conductive path (104) • in which the first layer (105), a layer stack (301) having a lower layer (110a) and an upper layer (110c) and a middle layer (110b) is produced from a first electrical insulating material, • in which through the layer stack (301) and the second hole (107) therethrough and in reaching a first recess (302) is generated in the substrate (102) • generating a plug (111) in which in the first recess (302) on the central layer (110b), wherein the first recess ...

Werner Pamler

Papers

Masque de gravure pour l'attaque sèche d'une structure d'électrode

Method for the creation of a layer system and layer system

A method for manufacturing a device and device having a metal layer and an insulation layer

Hohlraumstruktur und Verfahren zum Herstellen einer Hohlraumstruktur Cavity structure and method of making a hollow structure

A method of manufacturing a conductor path arrangement and interconnect arrangement