An object is to provide a method for manufacturing a semiconductor device, in which the number of photolithography steps can be reduced, the manufacturing process can be simplified, and manufacturing can be performed with high yield at low cost A method for manufacturing a semiconductor device includes the following steps: forming a semiconductor film; irradiating a laser beam by passing the laser beam through a photomask including a shield for shielding the laser beam; subliming a region which has been irradiated with the laser beam through a region in which the shield is not formed in the photomask in the semiconductor film; forming an island-shaped semiconductor film in such a way that a region which is not irradiated with the laser beam is not sublimed because it is a region in which the shield is formed in the photomask; forming a first electrode which is one of a source electrode and a drain electrode and a second electrode which is the other one of the source electrode and the drain electrode; forming a gate insulating film; and forming a gate electrode over the gate insulating film

Method for Manufacturing Semiconductor Device

A nonplanar semiconductor device and its method of fabrication is described. The nonplanar semiconductor device includes a semiconductor body having a top surface opposite a bottom surface formed above an insulating substrate wherein the semiconductor body has a pair laterally opposite sidewalls. A gate dielectric is formed on the top surface of the semiconductor body on the laterally opposite sidewalls of the semiconductor body and on at least a portion of the bottom surface of semiconductor body. A gate electrode is formed on the gate dielectric, on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of semiconductor body and beneath the gate dielectric on the bottom surface of the semiconductor body. A pair source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.

Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication

A method of a bulk tri-gate transistor having stained enhanced mobility and its method of fabrication. The present invention is a nonplanar transistor having a strained enhanced mobility and its method of fabrication. The transistor has a semiconductor body formed on a semiconductor substrate wherein the semiconductor body has a top surface on laterally opposite sidewalls. A semiconductor capping layer is formed on the top surface and on the sidewalls of the semiconductor body. A gate dielectric layer is formed on the semiconductor capping layer on the top surface of a semiconductor body and is formed on the capping layer on the sidewalls of the semiconductor body. A gate electrode having a pair of laterally opposite sidewalls is formed on and around the gate dielectric layer. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.

Bulk non-planar transistor having strained enhanced mobility and methods of fabrication

A contact architecture for nanoscale channel devices having contact structures coupling to and extending between source or drain regions of a device having a plurality of parallel semiconductor bodies. The contact structures being able to contact parallel semiconductor bodies having sub-lithographic pitch.

Block Contact Architectures for Nanoscale Channel Transistors

Described herein are a device utilizing a gate electrode material with a single work function for both the pMOS and nMOS transistors where the magnitude of the transistor threshold voltages is modified by semiconductor band engineering and article made thereby. Further described herein are methods of fabricating a device formed of complementary (pMOS and nMOS) transistors having semiconductor channel regions which have been band gap engineered to achieve a low threshold voltage.

CMOS devices with a single work function gate electrode and method of fabrication

A method of fabrication for self-aligned gallium arsenide transistors using metal implant masks is disclosed. Preferred embodiments include use of a dummy gate (150) made of aluminum (144) on top of titanium tungsten (142) as an implant mask for source (52) and drain (54) formation with the titanium tungsten (142) undercut so that deposited silicon dioxide (62) will form a self-aligned mask for the gate deposition after the dummy gate (150) is removed.

Self-aligned transistor method

A GaAs enhancement/depletion (E/D) MESFET 1-kbit static RAM has been fabricated on a 2-in GaAs-on-Si substrate. This is the most complex GaAs circuit reported to date for GaAs-on-Si material. The GaAs layer is grown on a

GaAs E/D MESFET 1-kbit static RAM fabricated on silicon substrate

Molecular-beam epitaxy (MBE) and ion implantation were used to fabricate GaAs/AlGaAs heterojunction bipolar transistors with buried wide bandgap emitters. Inverted-mode current gains of ∼ 100 were obtained, demonstrating the feasibility of this technology for I2L types of digital integrated circuits.

GaAs/AlGaAs heterojunction bipolar transistors for integrated circuit applications

The use of GaAs FETs as microwave switches is discussed, and the feasibility of such devices for applications requiring ultra low dc power consumption, low insertion loss, and bidirectionality is demonstrated. A discrete SPST switch consisting of two parallel-resonated single-gate GaAs FETs exhibited 0.5 db insertion loss with 25 db isolation at 8.5 GHz. The first monolithic SPDT switch incorporating parallel-resonated GaAs FETs is also reported.

Microwave switching with parallel-resonated GaAs FETS

Bipolar transistors and other electronic structures are fabricated on a gallium arsenide (GaAs) substrate to form an integrated circuit device. This integrated circuit device is made possible by development of an ion implant technique which uses an acceptor material to create a P type region, boron or protons to create insulating regions, and silicon or selenium to create an N type region. The use of an ion implant technique avoids the difficult problems encountered in diffusion methods, and, due to the precise control available with ion implantation, makes possible the fabrication of IC quality transistors consistently over a substrate. This same control enables the fabrication of integrated circuits with improved device packing density and reduced parasitic parameters.

William V. McLevige

Papers

Self-aligned transistor method

GaAs E/D MESFET 1-kbit static RAM fabricated on silicon substrate

GaAs/AlGaAs heterojunction bipolar transistors for integrated circuit applications

Microwave switching with parallel-resonated GaAs FETS

GaAs/GaAlAs Heterojunction bipolar integrated circuit devices