Xiaoyu Hu

TL;DR: In this paper, the main memory of the controller is not blocked by a complete address mapping table covering the entire memory device, instead such table is stored in the memory device itself, and only selected portions of address mapping information are buffered in a read cache (311) and a write cache (312), enabling an address mapping entry being evictable from the read cache without the need to update the related flash memory page storing such entry in the flash memory device.

TL;DR: In this article, the input data is stored in successive groups of data write locations, each group comprising write locations in a set of erasable blocks in each of a plurality of logical subdivisions of the solid state storage.

TL;DR: In this article, a method for reducing data loss comprising a first computing step for computing an intermediate result for each redundancy information entity of a redundancy set by processing respectively associated data information entities of a given data set on at least two main diagonals of a parity check matrix representing an error correction coding scheme.

TL;DR: In this paper, a logical array of rows and columns of data symbols is constructed from the input data to be stored in each group, which are respectively encoded in accordance with the first and second linear error correction codes to produce an encoded array.

TL;DR: In this article, it is determined that the page is to be promoted from the second cache to the first cache, if the reference count is greater than or equal to zero, and if the page was added to a Most Recently Used (LRU) end of the LRU list in the first cached.